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arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
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d4d986ee27
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d4e4129c31
6 changed files with 252 additions and 8 deletions
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@ -85,6 +85,7 @@ struct prcm_regs {
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u32 cm_div_h12_dpll_ddrphy;
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u32 cm_div_h13_dpll_ddrphy;
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u32 cm_ssc_deltamstep_dpll_ddrphy;
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u32 cm_clkmode_dpll_dsp;
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u32 cm_shadow_freq_config1;
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u32 cm_mpu_mpu_clkctrl;
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@ -143,6 +144,11 @@ struct prcm_regs {
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u32 cm_ssc_deltamstep_dpll_usb;
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u32 cm_ssc_modfreqdiv_dpll_usb;
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u32 cm_clkdcoldo_dpll_usb;
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u32 cm_clkmode_dpll_pcie_ref;
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u32 cm_clkmode_apll_pcie;
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u32 cm_idlest_apll_pcie;
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u32 cm_div_m2_apll_pcie;
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u32 cm_clkvcoldo_apll_pcie;
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u32 cm_clkmode_dpll_unipro;
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u32 cm_idlest_dpll_unipro;
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u32 cm_autoidle_dpll_unipro;
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@ -160,7 +166,7 @@ struct prcm_regs {
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u32 cm_l3_2_clkstctrl;
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u32 cm_l3_2_dynamicdep;
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u32 cm_l3_2_l3_2_clkctrl;
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u32 cm_l3_2_gpmc_clkctrl;
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u32 cm_l3_gpmc_clkctrl;
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u32 cm_l3_2_ocmc_ram_clkctrl;
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u32 cm_mpu_m3_clkstctrl;
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u32 cm_mpu_m3_staticdep;
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@ -205,6 +211,12 @@ struct prcm_regs {
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u32 cm_cam_clkstctrl;
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u32 cm_cam_iss_clkctrl;
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u32 cm_cam_fdif_clkctrl;
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u32 cm_cam_vip1_clkctrl;
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u32 cm_cam_vip2_clkctrl;
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u32 cm_cam_vip3_clkctrl;
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u32 cm_cam_lvdsrx_clkctrl;
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u32 cm_cam_csi1_clkctrl;
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u32 cm_cam_csi2_clkctrl;
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/* cm2.dss */
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u32 cm_dss_clkstctrl;
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@ -302,6 +314,8 @@ struct prcm_regs {
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u32 cm_wkup_bandgap_clkctrl;
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u32 cm_wkupaon_scrm_clkctrl;
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u32 cm_wkupaon_io_srcomp_clkctrl;
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u32 prm_rstctrl;
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u32 prm_rstst;
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u32 prm_vc_val_bypass;
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u32 prm_vc_cfg_i2c_mode;
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u32 prm_vc_cfg_i2c_clk;
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@ -485,6 +499,7 @@ extern struct prcm_regs const **prcm;
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extern struct prcm_regs const omap5_es1_prcm;
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extern struct prcm_regs const omap5_es2_prcm;
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extern struct prcm_regs const omap4_prcm;
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extern struct prcm_regs const dra7xx_prcm;
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extern struct dplls const **dplls_data;
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extern struct vcores_data const **omap_vcores;
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extern const u32 sys_clk_array[8];
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