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remoteproc: Add in SHARC loading for ADI SC5XX-family processors
This adds the ability to load ldr-formatted files to the SHARC coprocessors using the rproc interface. Only a minimal subset of rproc functionality is supported: loading and starting the remote core. Secure boot and signed ldr verification are not available at this time through the U-Boot interface. Co-developed-by: Greg Malysa <malysagreg@gmail.com> Signed-off-by: Greg Malysa <malysagreg@gmail.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com> Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com> Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com> Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
This commit is contained in:
Nathan Barrett-Morrison
Tom Rini
parent
072320d921
commit
d3bfe57788
4 changed files with 290 additions and 0 deletions
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@ -638,6 +638,7 @@ F: drivers/gpio/gpio-adi-adsp.c
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F: drivers/i2c/adi_i2c.c
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F: drivers/net/dwc_eth_qos_adi.c
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F: drivers/pinctrl/pinctrl-adi-adsp.c
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F: drivers/remoteproc/adi_sc5xx_rproc.c
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F: drivers/serial/serial_adi_uart4.c
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F: drivers/timer/adi_sc5xx_timer.c
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F: drivers/usb/musb-new/sc5xx.c
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@ -13,6 +13,7 @@ config REMOTEPROC
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depends on DM
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# Please keep the configuration alphabetically sorted.
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config K3_SYSTEM_CONTROLLER
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bool "Support for TI' K3 System Controller"
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select REMOTEPROC
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@ -22,6 +23,16 @@ config K3_SYSTEM_CONTROLLER
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help
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Say 'y' here to add support for TI' K3 System Controller.
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config REMOTEPROC_ADI_SC5XX
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bool "Support for ADI SC5xx SHARC cores"
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select REMOTEPROC
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depends on DM
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depends on ARCH_SC5XX
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depends on SYSCON
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help
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Say 'y' here to add support for loading code onto SHARC cores in
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an ADSP-SC5xx SoC from Analog Devices
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config REMOTEPROC_RENESAS_APMU
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bool "Support for Renesas R-Car Gen4 APMU start of CR52 processor"
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select REMOTEPROC
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@ -8,6 +8,7 @@ obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
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# Remote proc drivers - Please keep this list alphabetically sorted.
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obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
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obj-$(CONFIG_REMOTEPROC_ADI_SC5XX) += adi_sc5xx_rproc.o
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obj-$(CONFIG_REMOTEPROC_RENESAS_APMU) += renesas_apmu.o
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obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
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obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
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277
drivers/remoteproc/adi_sc5xx_rproc.c
Normal file
277
drivers/remoteproc/adi_sc5xx_rproc.c
Normal file
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@ -0,0 +1,277 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2022 - Analog Devices, Inc.
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*
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* Written and/or maintained by Timesys Corporation
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*
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* Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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* Contact: Greg Malysa <greg.malysa@timesys.com>
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*
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* Analog Devices SC5xx remoteproc driver for loading code onto SHARC cores
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*/
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#include <dm.h>
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#include <regmap.h>
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#include <remoteproc.h>
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#include <syscon.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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/* Register offsets */
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#ifdef CONFIG_SC58X
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#define ADI_RCU_REG_CTL 0x00
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#define ADI_RCU_REG_STAT 0x04
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#define ADI_RCU_REG_CRCTL 0x08
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#define ADI_RCU_REG_CRSTAT 0x0c
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#define ADI_RCU_REG_SIDIS 0x10
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#define ADI_RCU_REG_SISTAT 0x14
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#define ADI_RCU_REG_BCODE 0x1c
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#define ADI_RCU_REG_SVECT0 0x20
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#define ADI_RCU_REG_SVECT1 0x24
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#define ADI_RCU_REG_SVECT2 0x28
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#define ADI_RCU_REG_MSG 0x60
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#define ADI_RCU_REG_MSG_SET 0x64
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#define ADI_RCU_REG_MSG_CLR 0x68
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#else
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#define ADI_RCU_REG_CTL 0x00
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#define ADI_RCU_REG_STAT 0x04
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#define ADI_RCU_REG_CRCTL 0x08
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#define ADI_RCU_REG_CRSTAT 0x0c
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#define ADI_RCU_REG_SRRQSTAT 0x18
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#define ADI_RCU_REG_SIDIS 0x1c
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#define ADI_RCU_REG_SISTAT 0x20
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#define ADI_RCU_REG_SVECT_LCK 0x24
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#define ADI_RCU_REG_BCODE 0x28
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#define ADI_RCU_REG_SVECT0 0x2c
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#define ADI_RCU_REG_SVECT1 0x30
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#define ADI_RCU_REG_SVECT2 0x34
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#define ADI_RCU_REG_MSG 0x6c
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#define ADI_RCU_REG_MSG_SET 0x70
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#define ADI_RCU_REG_MSG_CLR 0x74
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#endif /* CONFIG_SC58X */
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/* Register bit definitions */
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#define ADI_RCU_CTL_SYSRST BIT(0)
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/* Bit values for the RCU0_MSG register */
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#define RCU0_MSG_C0IDLE 0x00000100 /* Core 0 Idle */
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#define RCU0_MSG_C1IDLE 0x00000200 /* Core 1 Idle */
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#define RCU0_MSG_C2IDLE 0x00000400 /* Core 2 Idle */
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#define RCU0_MSG_CRR0 0x00001000 /* Core 0 reset request */
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#define RCU0_MSG_CRR1 0x00002000 /* Core 1 reset request */
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#define RCU0_MSG_CRR2 0x00004000 /* Core 2 reset request */
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#define RCU0_MSG_C1ACTIVATE 0x00080000 /* Core 1 Activated */
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#define RCU0_MSG_C2ACTIVATE 0x00100000 /* Core 2 Activated */
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struct sc5xx_rproc_data {
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/* Address to load to svect when rebooting core */
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u32 load_addr;
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/* RCU parameters */
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struct regmap *rcu;
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u32 svect_offset;
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u32 coreid;
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};
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struct block_code_flag {
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u32 bcode:4, /* 0-3 */
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bflag_save:1, /* 4 */
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bflag_aux:1, /* 5 */
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breserved:1, /* 6 */
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bflag_forward:1, /* 7 */
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bflag_fill:1, /* 8 */
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bflag_quickboot:1, /* 9 */
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bflag_callback:1, /* 10 */
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bflag_init:1, /* 11 */
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bflag_ignore:1, /* 12 */
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bflag_indirect:1, /* 13 */
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bflag_first:1, /* 14 */
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bflag_final:1, /* 15 */
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bhdrchk:8, /* 16-23 */
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bhdrsign:8; /* 0xAD, 0xAC or 0xAB */
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};
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struct ldr_hdr {
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struct block_code_flag bcode_flag;
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u32 target_addr;
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u32 byte_count;
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u32 argument;
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};
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static int is_final(struct ldr_hdr *hdr)
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{
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return hdr->bcode_flag.bflag_final;
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}
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static int is_empty(struct ldr_hdr *hdr)
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{
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return hdr->bcode_flag.bflag_ignore || (hdr->byte_count == 0);
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}
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static int adi_valid_firmware(struct ldr_hdr *adi_ldr_hdr)
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{
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if (!adi_ldr_hdr->byte_count &&
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(adi_ldr_hdr->bcode_flag.bhdrsign == 0xAD ||
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adi_ldr_hdr->bcode_flag.bhdrsign == 0xAC ||
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adi_ldr_hdr->bcode_flag.bhdrsign == 0xAB))
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return 1;
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return 0;
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}
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static int sharc_load(struct udevice *dev, ulong addr, ulong size)
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{
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struct sc5xx_rproc_data *priv = dev_get_priv(dev);
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size_t offset;
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u8 *buf = (u8 *)addr;
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struct ldr_hdr *ldr = (struct ldr_hdr *)addr;
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struct ldr_hdr *block_hdr;
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struct ldr_hdr *next_hdr;
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if (!adi_valid_firmware(ldr)) {
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dev_err(dev, "Firmware at 0x%lx does not appear to be an LDR image\n", addr);
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dev_err(dev, "Note: Signed firmware is not currently supported\n");
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return -EINVAL;
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}
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do {
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block_hdr = (struct ldr_hdr *)buf;
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offset = sizeof(struct ldr_hdr) + (block_hdr->bcode_flag.bflag_fill ?
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0 : block_hdr->byte_count);
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next_hdr = (struct ldr_hdr *)(buf + offset);
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if (block_hdr->bcode_flag.bflag_first)
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priv->load_addr = (unsigned long)block_hdr->target_addr;
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if (!is_empty(block_hdr)) {
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if (block_hdr->bcode_flag.bflag_fill) {
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memset_io((void *)(phys_addr_t)block_hdr->target_addr,
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block_hdr->argument,
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block_hdr->byte_count);
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} else {
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memcpy_toio((void *)(phys_addr_t)block_hdr->target_addr,
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buf + sizeof(struct ldr_hdr),
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block_hdr->byte_count);
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}
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}
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if (is_final(block_hdr))
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break;
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buf += offset;
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} while (1);
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return 0;
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}
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static void sharc_reset(struct sc5xx_rproc_data *priv)
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{
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u32 coreid = priv->coreid;
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u32 val;
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/* First put core in reset.
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* Clear CRSTAT bit for given coreid.
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*/
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regmap_write(priv->rcu, ADI_RCU_REG_CRSTAT, 1 << coreid);
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/* Set SIDIS to disable the system interface */
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regmap_read(priv->rcu, ADI_RCU_REG_SIDIS, &val);
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regmap_write(priv->rcu, ADI_RCU_REG_SIDIS, val | (1 << (coreid - 1)));
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/*
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* Wait for access to coreX have been disabled and all the pending
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* transactions have completed
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*/
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udelay(50);
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/* Set CRCTL bit to put core in reset */
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regmap_read(priv->rcu, ADI_RCU_REG_CRCTL, &val);
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regmap_write(priv->rcu, ADI_RCU_REG_CRCTL, val | (1 << coreid));
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/* Poll until Core is in reset */
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while (!(regmap_read(priv->rcu, ADI_RCU_REG_CRSTAT, &val), val & (1 << coreid)))
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;
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/* Clear SIDIS to reenable the system interface */
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regmap_read(priv->rcu, ADI_RCU_REG_SIDIS, &val);
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regmap_write(priv->rcu, ADI_RCU_REG_SIDIS, val & ~(1 << (coreid - 1)));
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udelay(50);
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/* Take Core out of reset */
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regmap_read(priv->rcu, ADI_RCU_REG_CRCTL, &val);
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regmap_write(priv->rcu, ADI_RCU_REG_CRCTL, val & ~(1 << coreid));
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/* Wait for done */
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udelay(50);
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}
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static int sharc_start(struct udevice *dev)
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{
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struct sc5xx_rproc_data *priv = dev_get_priv(dev);
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/* Write load address to appropriate SVECT for core */
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regmap_write(priv->rcu, priv->svect_offset, priv->load_addr);
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sharc_reset(priv);
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/* Clear the IDLE bit when start the SHARC core */
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regmap_write(priv->rcu, ADI_RCU_REG_MSG_CLR, RCU0_MSG_C0IDLE << priv->coreid);
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/* Notify CCES */
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regmap_write(priv->rcu, ADI_RCU_REG_MSG_SET, RCU0_MSG_C1ACTIVATE << (priv->coreid - 1));
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return 0;
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}
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static const struct dm_rproc_ops sc5xx_ops = {
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.load = sharc_load,
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.start = sharc_start,
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};
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static int sc5xx_probe(struct udevice *dev)
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{
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struct sc5xx_rproc_data *priv = dev_get_priv(dev);
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u32 coreid;
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if (dev_read_u32(dev, "coreid", &coreid)) {
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dev_err(dev, "Missing property coreid\n");
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return -ENOENT;
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}
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priv->coreid = coreid;
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switch (coreid) {
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case 1:
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priv->svect_offset = ADI_RCU_REG_SVECT1;
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break;
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case 2:
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priv->svect_offset = ADI_RCU_REG_SVECT2;
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break;
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default:
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dev_err(dev, "Invalid value %d for coreid, must be 1 or 2\n", coreid);
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return -EINVAL;
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}
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priv->rcu = syscon_regmap_lookup_by_phandle(dev, "adi,rcu");
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if (IS_ERR(priv->rcu))
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return PTR_ERR(priv->rcu);
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dev_err(dev, "sc5xx remoteproc core %d available\n", priv->coreid);
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return 0;
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}
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static const struct udevice_id sc5xx_ids[] = {
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{ .compatible = "adi,sc5xx-rproc" },
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{ }
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};
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U_BOOT_DRIVER(adi_sc5xx_rproc) = {
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.name = "adi_sc5xx_rproc",
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.of_match = sc5xx_ids,
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.id = UCLASS_REMOTEPROC,
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.ops = &sc5xx_ops,
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.probe = sc5xx_probe,
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.priv_auto = sizeof(struct sc5xx_rproc_data),
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.flags = 0,
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};
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