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board: phytec: imx93: Add eeprom-based hardware introspection
The phyCORE-i.MX 93 is available in various variants. Relevant variant options for the spl/u-boot are: - with or without HS400 support for the eMMC - with 1GB ram chip, or 2GB ram chip The phyCORE's eeprom contains all information about the existing variant options. Add evaluation of the eeprom data to the spl/u-boot to enable/disable HS400 and to select the appropriate ram configuration at startup. Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Primoz Fiser <primoz.fiser@norik.com>
This commit is contained in:
Christoph Stoidner
Fabio Estevam
parent
29d4a73bd0
commit
d3b9b79968
11 changed files with 363 additions and 2 deletions
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@ -139,6 +139,13 @@
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&usdhc1 {
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bootph-pre-ram;
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bootph-some-ram;
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/*
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* Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
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*/
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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};
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&usdhc2 {
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@ -215,6 +222,48 @@
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MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
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>;
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};
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/*
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* Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
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* are added to imx93-phycore-som.dtsi
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*/
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
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>;
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};
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};
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&lpi2c3 {
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@ -305,4 +354,13 @@
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};
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};
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};
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eeprom@50 {
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bootph-pre-ram;
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bootph-some-ram;
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compatible = "atmel,24c32";
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reg = <0x50>;
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pagesize = <32>;
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vcc-supply = <&buck4>;
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};
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};
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@ -45,6 +45,8 @@ config TARGET_PHYCORE_IMX93
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bool "phycore_imx93"
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select IMX93
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select IMX9_LPDDR4X
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select OF_BOARD_FIXUP
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select OF_BOARD_SETUP
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endchoice
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@ -634,7 +634,7 @@ static int low_drive_freq_update(void *blob)
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_FIXUP
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#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
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#ifndef CONFIG_XPL_BUILD
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int board_fix_fdt(void *fdt)
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{
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@ -19,6 +19,14 @@ config PHYTEC_IMX8M_SOM_DETECTION
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Support of I2C EEPROM based SoM detection. Supported
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for PHYTEC i.MX8MM/i.MX8MP boards
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config PHYTEC_IMX93_SOM_DETECTION
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bool "Support SoM detection for i.MX93 PHYTEC platforms"
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depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION
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default y
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help
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Support of I2C EEPROM based SoM detection. Supported
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for PHYTEC i.MX93 based boards
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config PHYTEC_AM62_SOM_DETECTION
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bool "Support SoM detection for AM62x PHYTEC platforms"
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depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \
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@ -10,3 +10,4 @@ endif
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obj-y += phytec_som_detection.o phytec_som_detection_blocks.o
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obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/
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obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o
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obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o
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111
board/phytec/common/imx93_som_detection.c
Normal file
111
board/phytec/common/imx93_som_detection.c
Normal file
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@ -0,0 +1,111 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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* Author: Primoz Fiser <primoz.fiser@norik.com>
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*/
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#include <asm/arch/sys_proto.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <i2c.h>
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#include <u-boot/crc.h>
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#include "imx93_som_detection.h"
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extern struct phytec_eeprom_data eeprom_data;
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#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION)
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/* Check if the SoM is actually one of the following products:
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* - i.MX93
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*
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* Returns 0 in case it's a known SoM. Otherwise, returns 1.
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*/
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u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
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{
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u8 som;
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if (!data)
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data = &eeprom_data;
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/* Early API revisions are not supported */
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if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
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return 1;
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som = data->payload.data.data_api2.som_no;
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debug("%s: som id: %u\n", __func__, som);
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if (som == PHYTEC_IMX93_SOM && is_imx93())
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return 0;
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pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__);
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return 1;
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}
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/*
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* Filter PHYTEC i.MX93 SoM options by option index
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*
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* Returns:
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* - option value
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* - PHYTEC_EEPROM_INVAL when the data is invalid
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*
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*/
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u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
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enum phytec_imx93_option_index idx)
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{
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char *opt;
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u8 opt_id;
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if (!data)
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data = &eeprom_data;
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if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2)
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return PHYTEC_EEPROM_INVAL;
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opt = phytec_get_opt(data);
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if (opt)
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opt_id = PHYTEC_GET_OPTION(opt[idx]);
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else
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opt_id = PHYTEC_EEPROM_INVAL;
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debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id);
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return opt_id;
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}
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/*
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* Filter PHYTEC i.MX93 SoM voltage
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*
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* Returns:
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* - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3
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* - PHYTEC_EEPROM_INVAL when the data is invalid
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*
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*/
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enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data)
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{
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u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT);
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if (option == PHYTEC_EEPROM_INVAL)
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return PHYTEC_IMX93_VOLTAGE_INVALID;
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return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3;
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}
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#else
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inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data)
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{
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return 1;
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}
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inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
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enum phytec_imx93_option_index idx)
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{
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return PHYTEC_EEPROM_INVAL;
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}
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inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
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(struct phytec_eeprom_data *data)
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{
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return PHYTEC_EEPROM_INVAL;
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}
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#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */
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51
board/phytec/common/imx93_som_detection.h
Normal file
51
board/phytec/common/imx93_som_detection.h
Normal file
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@ -0,0 +1,51 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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* Author: Primoz Fiser <primoz.fiser@norik.com>
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*/
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#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
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#define _PHYTEC_IMX93_SOM_DETECTION_H
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#include "phytec_som_detection.h"
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#define PHYTEC_IMX93_SOM 77
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enum phytec_imx93_option_index {
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PHYTEC_IMX93_OPT_DDR = 0,
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PHYTEC_IMX93_OPT_EMMC = 1,
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PHYTEC_IMX93_OPT_CPU = 2,
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PHYTEC_IMX93_OPT_FREQ = 3,
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PHYTEC_IMX93_OPT_NPU = 4,
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PHYTEC_IMX93_OPT_DISP = 5,
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PHYTEC_IMX93_OPT_ETH = 6,
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PHYTEC_IMX93_OPT_FEAT = 7,
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PHYTEC_IMX93_OPT_TEMP = 8,
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PHYTEC_IMX93_OPT_BOOT = 9,
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PHYTEC_IMX93_OPT_LED = 10,
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PHYTEC_IMX93_OPT_EEPROM = 11,
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};
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enum phytec_imx93_voltage {
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PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
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PHYTEC_IMX93_VOLTAGE_3V3 = 0,
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PHYTEC_IMX93_VOLTAGE_1V8 = 1,
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};
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enum phytec_imx93_ddr_eeprom_code {
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PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
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PHYTEC_IMX93_LPDDR4X_512MB = 0,
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PHYTEC_IMX93_LPDDR4X_1GB = 1,
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PHYTEC_IMX93_LPDDR4X_2GB = 2,
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PHYTEC_IMX93_LPDDR4_512MB = 3,
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PHYTEC_IMX93_LPDDR4_1GB = 4,
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PHYTEC_IMX93_LPDDR4_2GB = 5,
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};
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u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
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u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
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enum phytec_imx93_option_index idx);
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enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
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(struct phytec_eeprom_data *data);
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#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
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@ -10,4 +10,32 @@ config SYS_VENDOR
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config SYS_CONFIG_NAME
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default "phycore_imx93"
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config PHYCORE_IMX93_RAM_TYPE_FIX
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bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting"
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default false
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help
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RAM type and size is being automatically detected with the help
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of the PHYTEC EEPROM introspection data.
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Set RAM type to a fix value instead.
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choice
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prompt "phyCORE-i.MX93 RAM type"
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depends on PHYCORE_IMX93_RAM_TYPE_FIX
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default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
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config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB
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bool "LPDDR4X 1GB RAM"
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help
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Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB
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for phyCORE-i.MX93.
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config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB
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bool "LPDDR4X 2GB RAM"
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help
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Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB
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for phyCORE-i.MX93.
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endchoice
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source "board/phytec/common/Kconfig"
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endif
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@ -1,10 +1,13 @@
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phyCORE-i.MX93
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M: Mathieu Othacehe <m.othacehe@gmail.com>
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R: Christoph Stoidner <c.stoidner@phytec.de>
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W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
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S: Maintained
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F: arch/arm/dts/imx93-phyboard-segin.dts
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F: arch/arm/dts/imx93-phycore-som.dtsi
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F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
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F: board/phytec/phycore_imx93/
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F: board/phytec/common/imx93_som_detection.c
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F: board/phytec/common/imx93_som_detection.h
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F: configs/imx93-phyboard-segin_defconfig
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F: include/configs/phycore_imx93.h
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@ -3,6 +3,7 @@
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Author: Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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*/
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#include <asm/arch-imx9/ccm_regs.h>
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@ -12,11 +13,21 @@
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <env.h>
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#include <fdt_support.h>
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#include "../common/imx93_som_detection.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define EEPROM_ADDR 0x50
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int board_init(void)
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{
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int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
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if (ret)
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printf("%s: EEPROM data init failed\n", __func__);
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return 0;
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}
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@ -40,3 +51,43 @@ int board_late_init(void)
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return 0;
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}
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static void emmc_fixup(void *blob, struct phytec_eeprom_data *data)
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{
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enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data);
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int offset;
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if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID)
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goto err;
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if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) {
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offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc",
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0x42850000);
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if (offset)
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fdt_delprop(blob, offset, "no-1-8-v");
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else
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goto err;
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}
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return;
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err:
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printf("Could not detect eMMC VDD-IO. Fall back to default.\n");
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}
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int board_fix_fdt(void *blob)
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{
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struct phytec_eeprom_data data;
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phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR);
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emmc_fixup(blob, &data);
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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emmc_fixup(blob, NULL);
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return 0;
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}
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@ -3,6 +3,7 @@
|
|||
* Copyright (C) 2023 PHYTEC Messtechnik GmbH
|
||||
* Author: Christoph Stoidner <c.stoidner@phytec.de>
|
||||
* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
|
||||
* Copyright (C) 2024 PHYTEC Messtechnik GmbH
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
|
|
@ -20,6 +21,8 @@
|
|||
#include <power/pca9450.h>
|
||||
#include <spl.h>
|
||||
|
||||
#include "../common/imx93_som_detection.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
|
|
@ -27,6 +30,13 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
* when pca9451a support is added.
|
||||
*/
|
||||
#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
|
||||
#define EEPROM_ADDR 0x50
|
||||
|
||||
/*
|
||||
* Prototypes of automatically generated ram config file
|
||||
*/
|
||||
void set_dram_timings_2gb_lpddr4x(void);
|
||||
void set_dram_timings_1gb_lpddr4x_900mhz(void);
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
|
|
@ -46,6 +56,44 @@ void spl_board_init(void)
|
|||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
int ret;
|
||||
enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
|
||||
|
||||
/* NOTE: In SPL lpi2c3 is mapped to bus 0 */
|
||||
ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
|
||||
if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
|
||||
goto out;
|
||||
|
||||
ret = phytec_imx93_detect(NULL);
|
||||
if (!ret)
|
||||
phytec_print_som_info(NULL);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) {
|
||||
if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB))
|
||||
ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB;
|
||||
else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB))
|
||||
ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB;
|
||||
} else {
|
||||
ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR);
|
||||
}
|
||||
|
||||
switch (ddr_opt) {
|
||||
case PHYTEC_IMX93_LPDDR4X_1GB:
|
||||
if (is_voltage_mode(VOLT_LOW_DRIVE))
|
||||
set_dram_timings_1gb_lpddr4x_900mhz();
|
||||
break;
|
||||
case PHYTEC_IMX93_LPDDR4X_2GB:
|
||||
set_dram_timings_2gb_lpddr4x();
|
||||
break;
|
||||
default:
|
||||
goto out;
|
||||
}
|
||||
ddr_init(&dram_timing);
|
||||
return;
|
||||
out:
|
||||
puts("Could not detect correct RAM type and size. Fall back to default.\n");
|
||||
if (is_voltage_mode(VOLT_LOW_DRIVE))
|
||||
set_dram_timings_1gb_lpddr4x_900mhz();
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue