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Update MTD to that of Linux 2.6.22.1
A lot changed in the Linux MTD code, since it was last ported from Linux to U-Boot. This patch takes U-Boot NAND support to the level of Linux 2.6.22.1 and will enable support for very large NAND devices (4KB pages) and ease the compatibility between U-Boot and Linux filesystems. This patch is tested on two custom boards with PPC and ARM processors running YAFFS in U-Boot and Linux using gcc-4.1.2 cross compilers. MAKEALL ppc/arm has some issues: * DOC/OneNand/nand_spl is not building (I have not tried porting these parts, and since I do not have any HW and I am not familiar with this code/HW I think its best left to someone else.) Except for the issues mentioned above, I have ported all drivers necessary to run MAKEALL ppc/arm without errors and warnings. Many drivers were trivial to port, but some were not so trivial. The following drivers must be examined carefully and maybe rewritten to some degree: cpu/ppc4xx/ndfc.c cpu/arm926ejs/davinci/nand.c board/delta/nand.c board/zylonite/nand.c Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Stig Olsen <stig.olsen@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
William Juul
Scott Wood
parent
cd82919e6c
commit
cfa460adfd
37 changed files with 4829 additions and 3436 deletions
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@ -2,114 +2,123 @@
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* linux/include/linux/mtd/nand.h
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*
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* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
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* $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*
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* Changelog:
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* 01-31-2000 DMW Created
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* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
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* so it can be used by other NAND flash device
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* drivers. I also changed the copyright since none
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* of the original contents of this file are specific
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* to DoC devices. David can whack me with a baseball
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* bat later if I did something naughty.
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* 10-11-2000 SJH Added private NAND flash structure for driver
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* 10-24-2000 SJH Added prototype for 'nand_scan' function
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* 10-29-2001 TG changed nand_chip structure to support
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* hardwarespecific function for accessing control lines
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* 02-21-2002 TG added support for different read/write adress and
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* ready/busy line access function
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* 02-26-2002 TG added chip_delay to nand_chip structure to optimize
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* command delay times for different chips
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* 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
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* defines in jffs2/wbuf.c
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* 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
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* CONFIG_MTD_NAND_ECC_JFFS2 is not set
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* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
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*
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* 08-29-2002 tglx nand_chip structure: data_poi for selecting
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* internal / fs-driver buffer
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* support for 6byte/512byte hardware ECC
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* read_ecc, write_ecc extended for different oob-layout
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* oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
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* NAND_YAFFS_OOB
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* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
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* Split manufacturer and device ID structures
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*
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* 02-08-2004 tglx added option field to nand structure for chip anomalities
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* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
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* update of nand_chip structure description
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* Changelog:
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* See git changelog.
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*/
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#ifndef __LINUX_MTD_NAND_H
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#define __LINUX_MTD_NAND_H
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#include <linux/mtd/compat.h>
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/* XXX U-BOOT XXX */
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#if 0
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#include <linux/wait.h>
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#include <linux/spinlock.h>
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#include <linux/mtd/mtd.h>
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#endif
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#include "config.h"
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#include "linux/mtd/compat.h"
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#include "linux/mtd/mtd.h"
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struct mtd_info;
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/* Scan and identify a NAND device */
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extern int nand_scan (struct mtd_info *mtd, int max_chips);
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/* Separate phases of nand_scan(), allowing board driver to intervene
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* and override command or ECC setup according to flash type */
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extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
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extern int nand_scan_tail(struct mtd_info *mtd);
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/* Free resources held by the NAND device */
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extern void nand_release (struct mtd_info *mtd);
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/* Read raw data from the device without ECC */
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extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
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/* Internal helper for board drivers which need to override command function */
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extern void nand_wait_ready(struct mtd_info *mtd);
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/* The maximum number of NAND chips in an array */
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#ifndef NAND_MAX_CHIPS
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#define NAND_MAX_CHIPS 8
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#endif
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/* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 64
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#define NAND_MAX_OOBSIZE 128
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#define NAND_MAX_PAGESIZE 4096
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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*/
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*
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* These are bits which can be or'ed to set/clear multiple
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* bits in one go.
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*/
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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#define NAND_NCE 0x01
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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#define NAND_CLE 0x02
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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/* Set write protection by setting WP to high. Not used! */
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#define NAND_CTL_SETWP 7
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/* Clear write protection by setting WP to low. Not used! */
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#define NAND_CTL_CLRWP 8
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#define NAND_ALE 0x04
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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
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#define NAND_CTRL_CHANGE 0x80
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_RNDOUT 5
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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#define NAND_CMD_NONE -1
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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/*
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* Constants for ECC_MODES
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*/
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/* No ECC. Usage is not recommended ! */
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#define NAND_ECC_NONE 0
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/* Software ECC 3 byte ECC per 256 Byte data */
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#define NAND_ECC_SOFT 1
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/* Hardware ECC 3 byte ECC per 256 Byte data */
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#define NAND_ECC_HW3_256 2
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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#define NAND_ECC_HW3_512 3
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/* Hardware ECC 6 byte ECC per 512 Byte data */
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#define NAND_ECC_HW6_512 4
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/* Hardware ECC 8 byte ECC per 512 Byte data */
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#define NAND_ECC_HW8_512 6
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/* Hardware ECC 12 byte ECC per 2048 Byte data */
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#define NAND_ECC_HW12_2048 7
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typedef enum {
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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} nand_ecc_modes_t;
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/*
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* Constants for Hardware ECC
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*/
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*/
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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@ -146,6 +146,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
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/* Enable Hardware ECC before syndrom is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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#define NAND_GET_DEVICE 0x80
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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@ -165,6 +169,17 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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#define BBT_AUTO_REFRESH 0x00000080
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/* Chip does not require ready check on read. True
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* for all large page devices, as they do not support
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* autoincrement.*/
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#define NAND_NO_READRDY 0x00000100
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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@ -183,18 +198,18 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
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/* Use a flash based bad block table. This option is passed to the
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* default bad block table function. */
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#define NAND_USE_FLASH_BBT 0x00010000
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/* The hw ecc generator provides a syndrome instead a ecc value on read
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* This can only work if we have the ecc bytes directly behind the
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* data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
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#define NAND_HWECC_SYNDROME 0x00020000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00020000
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/* This option is defined if the board driver allocates its own buffers
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(e.g. because it needs them DMA-coherent */
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#define NAND_OWN_BUFFERS 0x00040000
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/* Options set by nand scan */
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/* Nand scan has allocated oob_buf */
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#define NAND_OOBBUF_ALLOC 0x40000000
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/* Nand scan has allocated data_buf */
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#define NAND_DATABUF_ALLOC 0x80000000
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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/* Cell info constants */
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#define NAND_CI_CHIPNR_MSK 0x03
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#define NAND_CI_CELLTYPE_MSK 0x0C
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/*
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* nand_state_t - chip states
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@ -207,135 +222,216 @@ typedef enum {
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FL_ERASING,
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FL_SYNCING,
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FL_CACHEDPRG,
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FL_PM_SUSPENDED,
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} nand_state_t;
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/* Keep gcc happy */
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struct nand_chip;
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#if 0
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/**
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
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* @lock: protection lock
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in progress
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* used instead of the per chip wait queue when a hw controller is available
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*/
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struct nand_hw_control {
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spinlock_t lock;
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struct nand_chip *active;
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};
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#if 0
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spinlock_t lock;
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wait_queue_head_t wq;
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#endif
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struct nand_chip *active;
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};
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/**
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* struct nand_ecc_ctrl - Control structure for ecc
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* @mode: ecc mode
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* @steps: number of ecc steps per page
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* @size: data bytes per ecc step
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* @bytes: ecc bytes per step
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* @total: total number of ecc bytes per page
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* @prepad: padding information for syndrome based ecc generators
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* @postpad: padding information for syndrome based ecc generators
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* @layout: ECC layout control struct pointer
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* @hwctl: function to control hardware ecc generator. Must only
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* be provided if an hardware ECC is available
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* @calculate: function for ecc calculation or readback from ecc hardware
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* @correct: function for ecc correction, matching to ecc generator (sw/hw)
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* @read_page_raw: function to read a raw page without ECC
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* @write_page_raw: function to write a raw page without ECC
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* @read_page: function to read a page according to the ecc generator requirements
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* @write_page: function to write a page according to the ecc generator requirements
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* @read_oob: function to read chip OOB data
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* @write_oob: function to write chip OOB data
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*/
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struct nand_ecc_ctrl {
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nand_ecc_modes_t mode;
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int steps;
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int size;
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int bytes;
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int total;
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int prepad;
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int postpad;
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struct nand_ecclayout *layout;
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void (*hwctl)(struct mtd_info *mtd, int mode);
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int (*calculate)(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code);
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int (*correct)(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page_raw)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf);
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void (*write_page_raw)(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf);
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void (*write_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_oob)(struct mtd_info *mtd,
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struct nand_chip *chip,
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int page,
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int sndcmd);
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int (*write_oob)(struct mtd_info *mtd,
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struct nand_chip *chip,
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int page);
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};
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/**
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* struct nand_buffers - buffer structure for read/write
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* @ecccalc: buffer for calculated ecc
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* @ecccode: buffer for ecc read from flash
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* @databuf: buffer for data - dynamically sized
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*
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* Do not change the order of buffers. databuf and oobrbuf must be in
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* consecutive order.
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*/
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struct nand_buffers {
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uint8_t ecccalc[NAND_MAX_OOBSIZE];
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uint8_t ecccode[NAND_MAX_OOBSIZE];
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uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
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};
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
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* @read_byte: [REPLACEABLE] read one byte from the chip
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* @write_byte: [REPLACEABLE] write one byte to the chip
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* @read_word: [REPLACEABLE] read one word from the chip
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* @write_word: [REPLACEABLE] write one word to the chip
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* @write_buf: [REPLACEABLE] write data from the buffer to the chip
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* @read_buf: [REPLACEABLE] read data from the chip into the buffer
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
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* @select_chip: [REPLACEABLE] select chip nr
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* @block_bad: [REPLACEABLE] check, if the block is bad
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* @block_markbad: [REPLACEABLE] mark the block bad
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* @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
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* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
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* ALE/CLE/nCE. Also used to write command and address
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
|
||||
* If set to NULL no access to ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register
|
||||
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
|
||||
* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
|
||||
* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
|
||||
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
|
||||
* be provided if a hardware ECC is available
|
||||
* @ecc: [BOARDSPECIFIC] ecc control ctructure
|
||||
* @buffers: buffer structure for read/write
|
||||
* @hwcontrol: platform-specific hardware control structure
|
||||
* @ops: oob operation operands
|
||||
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
|
||||
* @scan_bbt: [REPLACEABLE] function to scan bad block table
|
||||
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
|
||||
* @eccsize: [INTERN] databytes used per ecc-calculation
|
||||
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
|
||||
* @eccsteps: [INTERN] number of ecc calculation steps per page
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
|
||||
* @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
|
||||
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
|
||||
* @state: [INTERN] the current state of the NAND device
|
||||
* @oob_poi: poison value buffer
|
||||
* @page_shift: [INTERN] number of address bits in a page (column address bits)
|
||||
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
||||
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
||||
* @chip_shift: [INTERN] number of address bits in one chip
|
||||
* @data_buf: [INTERN] internal buffer for one page + oob
|
||||
* @oob_buf: [INTERN] oob buffer for one eraseblock
|
||||
* @datbuf: [INTERN] internal buffer for one page + oob
|
||||
* @oobbuf: [INTERN] oob buffer for one eraseblock
|
||||
* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
|
||||
* @data_poi: [INTERN] pointer to a data buffer
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
|
||||
* special functionality. See the defines for further explanation
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob area
|
||||
* @cellinfo: [INTERN] MLC/multichip data from chip ident
|
||||
* @numchips: [INTERN] number of physical chips
|
||||
* @chipsize: [INTERN] the size of one chip for multichip arrays
|
||||
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
||||
* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
|
||||
* @autooob: [REPLACEABLE] the default (auto)placement scheme
|
||||
* @subpagesize: [INTERN] holds the subpagesize
|
||||
* @ecclayout: [REPLACEABLE] the default ecc placement scheme
|
||||
* @bbt: [INTERN] bad block table pointer
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
|
||||
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
|
||||
* @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller structure
|
||||
* which is shared among multiple independend devices
|
||||
* @priv: [OPTIONAL] pointer to private chip date
|
||||
* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
|
||||
* (determine if errors are correctable)
|
||||
* @write_page: [REPLACEABLE] High-level page write function
|
||||
*/
|
||||
|
||||
struct nand_chip {
|
||||
void __iomem *IO_ADDR_R;
|
||||
void __iomem *IO_ADDR_W;
|
||||
|
||||
u_char (*read_byte)(struct mtd_info *mtd);
|
||||
void (*write_byte)(struct mtd_info *mtd, u_char byte);
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_word)(struct mtd_info *mtd, u16 word);
|
||||
|
||||
void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
|
||||
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
|
||||
int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
|
||||
int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
|
||||
void (*enable_hwecc)(struct mtd_info *mtd, int mode);
|
||||
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int eccmode;
|
||||
int eccsize;
|
||||
int eccbytes;
|
||||
int eccsteps;
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
|
||||
int chip_delay;
|
||||
#if 0
|
||||
spinlock_t chip_lock;
|
||||
wait_queue_head_t wq;
|
||||
nand_state_t state;
|
||||
#endif
|
||||
unsigned int options;
|
||||
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
u_char *data_buf;
|
||||
u_char *oob_buf;
|
||||
int oobdirty;
|
||||
u_char *data_poi;
|
||||
unsigned int options;
|
||||
int badblockpos;
|
||||
int numchips;
|
||||
unsigned long chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
struct nand_oobinfo *autooob;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
|
||||
nand_state_t state;
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
|
||||
struct nand_ecc_ctrl ecc;
|
||||
struct nand_buffers *buffers;
|
||||
|
||||
struct nand_hw_control hwcontrol;
|
||||
|
||||
struct mtd_oob_ops ops;
|
||||
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
struct nand_hw_control *controller;
|
||||
|
||||
void *priv;
|
||||
};
|
||||
|
||||
|
|
@ -348,11 +444,11 @@ struct nand_chip {
|
|||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
|
||||
/**
|
||||
* struct nand_flash_dev - NAND Flash Device ID Structure
|
||||
*
|
||||
* @name: Identify the device type
|
||||
* @id: device ID code
|
||||
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
|
||||
|
|
@ -403,7 +499,7 @@ extern struct nand_manufacturers nand_manuf_ids[];
|
|||
* blocks is reserved at the end of the device where the tables are
|
||||
* written.
|
||||
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
|
||||
* bad) block in the stored bbt
|
||||
* bad) block in the stored bbt
|
||||
* @pattern: pattern to identify bad block table or factory marked good /
|
||||
* bad blocks, can be NULL, if len = 0
|
||||
*
|
||||
|
|
@ -417,11 +513,11 @@ struct nand_bbt_descr {
|
|||
int pages[NAND_MAX_CHIPS];
|
||||
int offs;
|
||||
int veroffs;
|
||||
uint8_t version[NAND_MAX_CHIPS];
|
||||
uint8_t version[NAND_MAX_CHIPS];
|
||||
int len;
|
||||
int maxblocks;
|
||||
int reserved_block_code;
|
||||
uint8_t *pattern;
|
||||
uint8_t *pattern;
|
||||
};
|
||||
|
||||
/* Options for the bad block table descriptors */
|
||||
|
|
@ -433,7 +529,7 @@ struct nand_bbt_descr {
|
|||
#define NAND_BBT_4BIT 0x00000004
|
||||
#define NAND_BBT_8BIT 0x00000008
|
||||
/* The bad block table is in the last good block of the device */
|
||||
#define NAND_BBT_LASTBLOCK 0x00000010
|
||||
#define NAND_BBT_LASTBLOCK 0x00000010
|
||||
/* The bbt is at the given page, else we must scan for the bbt */
|
||||
#define NAND_BBT_ABSPAGE 0x00000020
|
||||
/* The bbt is at the given page, else we must scan for the bbt */
|
||||
|
|
@ -456,13 +552,16 @@ struct nand_bbt_descr {
|
|||
#define NAND_BBT_SCAN2NDPAGE 0x00004000
|
||||
|
||||
/* The maximum number of blocks to scan for a bbt */
|
||||
#define NAND_BBT_SCAN_MAXBLOCKS 4
|
||||
#define NAND_BBT_SCAN_MAXBLOCKS 4
|
||||
|
||||
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
|
||||
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
|
||||
extern int nand_default_bbt (struct mtd_info *mtd);
|
||||
extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
|
||||
extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
|
||||
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
|
||||
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
|
||||
extern int nand_default_bbt(struct mtd_info *mtd);
|
||||
extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
|
||||
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
||||
int allowbbt);
|
||||
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
size_t * retlen, uint8_t * buf);
|
||||
|
||||
/*
|
||||
* Constants for oob configuration
|
||||
|
|
@ -470,4 +569,67 @@ extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int
|
|||
#define NAND_SMALL_BADBLOCK_POS 5
|
||||
#define NAND_LARGE_BADBLOCK_POS 0
|
||||
|
||||
/**
|
||||
* struct platform_nand_chip - chip level device structure
|
||||
* @nr_chips: max. number of chips to scan for
|
||||
* @chip_offset: chip number offset
|
||||
* @nr_partitions: number of partitions pointed to by partitions (or zero)
|
||||
* @partitions: mtd partition list
|
||||
* @chip_delay: R/B delay value in us
|
||||
* @options: Option flags, e.g. 16bit buswidth
|
||||
* @ecclayout: ecc layout info structure
|
||||
* @part_probe_types: NULL-terminated array of probe types
|
||||
* @priv: hardware controller specific settings
|
||||
*/
|
||||
struct platform_nand_chip {
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct platform_nand_ctrl - controller level device structure
|
||||
* @hwcontrol: platform specific hardware control structure
|
||||
* @dev_ready: platform specific function to read ready/busy pin
|
||||
* @select_chip: platform specific chip select function
|
||||
* @cmd_ctrl: platform specific function for controlling
|
||||
* ALE/CLE/nCE. Also used to write command and address
|
||||
* @priv: private data to transport driver specific settings
|
||||
*
|
||||
* All fields are optional and depend on the hardware driver requirements
|
||||
*/
|
||||
struct platform_nand_ctrl {
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct platform_nand_data - container structure for platform-specific data
|
||||
* @chip: chip level chip structure
|
||||
* @ctrl: controller level device structure
|
||||
*/
|
||||
struct platform_nand_data {
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
};
|
||||
|
||||
/* Some helpers to access the data structures */
|
||||
static inline
|
||||
struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
return chip->priv;
|
||||
}
|
||||
|
||||
#endif /* __LINUX_MTD_NAND_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue