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common: Drop linux/bitops.h from common header

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Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2020-05-10 11:40:13 -06:00 • committed by Tom Rini
parent f09f1ecbe7
commit cd93d625fd
749 changed files with 940 additions and 6 deletions
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1
arch/mips/mach-mscc/cpu.c
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@ -5,6 +5,7 @@
#include <common.h>
#include <init.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/types.h>

1
arch/mips/mach-mscc/gpio.c
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@ -5,6 +5,7 @@
#include <common.h>
#include <asm/io.h>
#include <linux/bitops.h>
void mscc_gpio_set_alternate(int gpio, int mode)
{

1
arch/mips/mach-mscc/include/mach/ddr.h
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@ -9,6 +9,7 @@
#include <asm/cacheops.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <linux/bitops.h>
#include <mach/common.h>
#define MIPS_VCOREIII_MEMORY_DDR3

2
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h
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@ -6,6 +6,8 @@
#ifndef _MSCC_JR2_DEVCPU_GCB_H_
#define _MSCC_JR2_DEVCPU_GCB_H_
#include <linux/bitops.h>
#define PERF_GPR 0x4
#define PERF_SOFT_RST 0x8

2
arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h
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@ -6,6 +6,8 @@
#ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_
#include <linux/bitops.h>
#define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36))
#define MIIM_MII_CMD(gi) (0xd0 + (gi * 36))
#define MIIM_MII_DATA(gi) (0xd4 + (gi * 36))

2
arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h
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@ -6,6 +6,8 @@
#ifndef _MSCC_JR2_ICPU_CFG_H_
#define _MSCC_JR2_ICPU_CFG_H_
#include <linux/bitops.h>
#define ICPU_GPR(x) (0x4 * (x))
#define ICPU_GPR_RSZ 0x4

1
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
#define _MSCC_OCELOT_DEVCPU_GCB_H_
#include <linux/bitops.h>
#define PERF_SOFT_RST 0x90
#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)

1
arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h
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@ -8,6 +8,7 @@
#ifndef _MSCC_LUTON_MIIM_REGS_H_
#define _MSCC_LUTON_MIIM_REGS_H_
#include <linux/bitops.h>
#define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36))
#define MIIM_MII_CMD(gi) (0xa8 + (gi * 36))
#define MIIM_MII_DATA(gi) (0xac + (gi * 36))

1
arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_OCELOT_ICPU_CFG_H_
#define _MSCC_OCELOT_ICPU_CFG_H_
#include <linux/bitops.h>
#define ICPU_GPR(x) (0x4 * (x))
#define ICPU_GPR_RSZ 0x4

1
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_OCELOT_DEVCPU_GCB_H_
#define _MSCC_OCELOT_DEVCPU_GCB_H_
#include <linux/bitops.h>
#define PERF_SOFT_RST 0x8
#define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2)

1
arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_
#include <linux/bitops.h>
#define MIIM_MII_STATUS(gi) (0x9c + (gi * 36))
#define MIIM_MII_CMD(gi) (0xa4 + (gi * 36))
#define MIIM_MII_DATA(gi) (0xa8 + (gi * 36))

1
arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_OCELOT_ICPU_CFG_H_
#define _MSCC_OCELOT_ICPU_CFG_H_
#include <linux/bitops.h>
#define ICPU_GPR(x) (0x4 * (x))
#define ICPU_GPR_RSZ 0x4

1
arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVAL_DEVCPU_GCB_H_
#define _MSCC_SERVAL_DEVCPU_GCB_H_
#include <linux/bitops.h>
#define CHIP_ID 0x0
#define PERF_GPR 0x4

1
arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_
#include <linux/bitops.h>
#define MIIM_MII_STATUS(gi) (0x5c + (gi * 36))
#define MIIM_MII_CMD(gi) (0x64 + (gi * 36))
#define MIIM_MII_DATA(gi) (0x68 + (gi * 36))

1
arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVAL_ICPU_CFG_H_
#define _MSCC_SERVAL_ICPU_CFG_H_
#include <linux/bitops.h>
#define ICPU_GPR(x) (0x4 * (x))
#define ICPU_GPR_RSZ 0x8

1
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVALT_DEVCPU_GCB_H_
#define _MSCC_SERVALT_DEVCPU_GCB_H_
#include <linux/bitops.h>
#define PERF_GPR 0x4
#define PERF_SOFT_RST 0x8

1
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
#define _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_
#include <linux/bitops.h>
#define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36))
#define MIIM_MII_CMD(gi) (0xcc + (gi * 36))
#define MIIM_MII_DATA(gi) (0xd0 + (gi * 36))

1
arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h
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@ -6,6 +6,7 @@
#ifndef _MSCC_SERVALT_ICPU_CFG_H_
#define _MSCC_SERVALT_ICPU_CFG_H_
#include <linux/bitops.h>
#define ICPU_GPR(x) (0x4 * (x))
#define ICPU_GPR_RSZ 0x8

1
arch/mips/mach-mscc/include/mach/tlb.h
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@ -7,6 +7,7 @@
#define __ASM_MACH_TLB_H
#include <asm/mipsregs.h>
#include <linux/bitops.h>
#include <mach/common.h>
#include <linux/sizes.h>