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Merge branch '2023-05-30-TI-fixes-Apple-M2-support'

Browse source 
- Fixes for some TI K3 platforms and merge the Apple M2 support I had
  intended to pick up earlier.
This commit is contained in:
Tom Rini 2023-05-30 16:23:41 -04:00
commit cb4437e530
13 changed files with 268 additions and 435 deletions
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2
MAINTAINERS
View file

@ -1496,8 +1496,6 @@ F: configs/k2g_hs_evm_defconfig
F: configs/k2l_hs_evm_defconfig F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig F: configs/am65x_hs_evm_a53_defconfig
F: configs/j721e_hs_evm_a72_defconfig
F: configs/j721e_hs_evm_r5_defconfig
TPM DRIVERS TPM DRIVERS
M: Ilias Apalodimas <ilias.apalodimas@linaro.org> M: Ilias Apalodimas <ilias.apalodimas@linaro.org>

109
arch/arm/mach-apple/board.c
View file

@ -343,6 +343,107 @@ static struct mm_region t6002_mem_map[] = {
} }
}; };
/* Apple M2 Pro/Max */
static struct mm_region t6020_mem_map[] = {
{
/* I/O */
.virt = 0x280000000,
.phys = 0x280000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x340000000,
.phys = 0x340000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x380000000,
.phys = 0x380000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5a0000000,
.phys = 0x5a0000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5c0000000,
.phys = 0x5c0000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x700000000,
.phys = 0x700000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xb00000000,
.phys = 0xb00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xf00000000,
.phys = 0xf00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x1300000000,
.phys = 0x1300000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* RAM */
.virt = 0x10000000000,
.phys = 0x10000000000,
.size = 16UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* Framebuffer */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map; struct mm_region *mem_map;
int board_init(void) int board_init(void)
@ -379,12 +480,14 @@ void build_mem_map(void)
if (of_machine_is_compatible("apple,t8103") || if (of_machine_is_compatible("apple,t8103") ||
of_machine_is_compatible("apple,t8112")) of_machine_is_compatible("apple,t8112"))
mem_map = t8103_mem_map; mem_map = t8103_mem_map;
else if (of_machine_is_compatible("apple,t6000")) else if (of_machine_is_compatible("apple,t6000") ||
mem_map = t6000_mem_map; of_machine_is_compatible("apple,t6001"))
else if (of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map; mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6002")) else if (of_machine_is_compatible("apple,t6002"))
mem_map = t6002_mem_map; mem_map = t6002_mem_map;
else if (of_machine_is_compatible("apple,t6020") ||
of_machine_is_compatible("apple,t6021"))
mem_map = t6020_mem_map;
else else
panic("Unsupported SoC\n"); panic("Unsupported SoC\n");

6
arch/arm/mach-k3/Kconfig
View file

@ -52,7 +52,8 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE config SYS_K3_MCU_SCRATCHPAD_BASE
hex hex
default 0x40280000 if SOC_K3_AM654 default 0x40280000 if SOC_K3_AM654
default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 default 0x40280000 if SOC_K3_J721S2
default 0x41cff9fc if SOC_K3_J721E
help help
Describes the base address of MCU Scratchpad RAM. Describes the base address of MCU Scratchpad RAM.
@ -140,8 +141,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
config K3_SYSFW_IMAGE_SIZE_MAX config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob" int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW depends on K3_LOAD_SYSFW
default 163840 if SOC_K3_AM625 || SOC_K3_AM62A7 default 280000
default 278000
help help
Amount of memory (in bytes) reserved through dynamic allocation at Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image runtime for loading the combined System Firmware and configuration image

5
arch/arm/mach-k3/common.c
View file

@ -347,8 +347,13 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE)) if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE))
#endif #endif
{ {
ti_secure_image_check_binary(p_image, p_size);
ti_secure_image_post_process(p_image, p_size); ti_secure_image_post_process(p_image, p_size);
} }
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
else
ti_secure_image_check_binary(p_image, p_size);
#endif
} }
#endif #endif

1
arch/arm/mach-k3/common.h
View file

@ -41,3 +41,4 @@ enum k3_device_type get_device_type(void);
void ti_secure_image_post_process(void **p_image, size_t *p_size); void ti_secure_image_post_process(void **p_image, size_t *p_size);
struct ti_sci_handle *get_ti_sci_handle(void); struct ti_sci_handle *get_ti_sci_handle(void);
void do_board_detect(void); void do_board_detect(void);
void ti_secure_image_check_binary(void **p_image, size_t *p_size);

2
arch/arm/mach-k3/config.mk
View file

@ -68,6 +68,8 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1 $(SPL_ITS): export IS_HS=1
INPUTS-y += tispl.bin_HS INPUTS-y += tispl.bin_HS
INPUTS-y += tispl.bin
tispl.bin: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST)))
else else
SPL_ITS := u-boot-spl-k3.its SPL_ITS := u-boot-spl-k3.its
INPUTS-y += tispl.bin INPUTS-y += tispl.bin

32
arch/arm/mach-k3/security.c
View file

@ -38,19 +38,16 @@ static size_t ti_secure_cert_length(void *p_image)
return seq_length + 4; return seq_length + 4;
} }
void ti_secure_image_post_process(void **p_image, size_t *p_size) void ti_secure_image_check_binary(void **p_image, size_t *p_size)
{ {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
size_t cert_length;
u64 image_addr;
u32 image_size; u32 image_size;
int ret; size_t cert_length;
image_size = *p_size; image_size = *p_size;
if (!image_size) if (!image_size) {
debug("%s: Image size is %d\n", __func__, image_size);
return; return;
}
if (get_device_type() == K3_DEVICE_TYPE_GP) { if (get_device_type() == K3_DEVICE_TYPE_GP) {
if (ti_secure_cert_detected(*p_image)) { if (ti_secure_cert_detected(*p_image)) {
@ -78,6 +75,25 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
"This will fail on Security Enforcing(HS-SE) devices\n"); "This will fail on Security Enforcing(HS-SE) devices\n");
return; return;
} }
}
void ti_secure_image_post_process(void **p_image, size_t *p_size)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
u64 image_addr;
u32 image_size;
int ret;
image_size = *p_size;
if (!image_size) {
debug("%s: Image size is %d\n", __func__, image_size);
return;
}
if (get_device_type() != K3_DEVICE_TYPE_HS_SE &&
get_device_type() != K3_DEVICE_TYPE_HS_FS)
return;
/* Clean out image so it can be seen by system firmware */ /* Clean out image so it can be seen by system firmware */
image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL); image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL);

3
configs/j721e_evm_a72_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_K3=y CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y CONFIG_SPL_GPIO=y
@ -32,7 +33,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7 CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

11
configs/j721e_evm_r5_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_K3=y CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y CONFIG_SPL_GPIO=y
@ -20,10 +21,16 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0xf59f0
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y CONFIG_SPL_SPI=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
@ -31,9 +38,9 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_MAX_SIZE=0xf59f0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R=y

209
configs/j721e_hs_evm_a72_defconfig
View file

@ -1,209 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlay_${boot}; run run_fit"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_MAXARGS=64
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
CONFIG_CMD_UBI=y
CONFIG_MMC_SPEED_MODE_SET=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y

176
configs/j721e_hs_evm_r5_defconfig
View file

@ -1,176 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_DFU=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_SHOW_PROGRESS=0
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_HBMC_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65941=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_TPS65941=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_HAS_CQSPI_REF_CLK=y
CONFIG_CQSPI_REF_CLK=133333333
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y

43
doc/board/ti/j721e_evm.rst
View file

@ -268,6 +268,49 @@ Image formats:
| +-------------------+ | | +-------------------+ |
+-----------------------+ +-----------------------+
R5 Memory Map:
--------------
.. list-table::
:widths: 16 16 16
:header-rows: 1
* - Region
- Start Address
- End Address
* - SPL
- 0x41c00000
- 0x41c40000
* - EMPTY
- 0x41c40000
- 0x41c81920
* - STACK
- 0x41c85920
- 0x41c81920
* - Global data
- 0x41c859f0
- 0x41c85920
* - Heap
- 0x41c859f0
- 0x41cf59f0
* - BSS
- 0x41cf59f0
- 0x41cff9f0
* - MCU Scratchpad
- 0x41cff9fc
- 0x41cffbfc
* - ROM DATA
- 0x41cffbfc
- 0x41cfffff
OSPI: OSPI:
----- -----
ROM supports booting from OSPI from offset 0x0. ROM supports booting from OSPI from offset 0x0.

102
drivers/pci/pcie_apple.c
View file

@ -37,14 +37,18 @@
#define CORE_RC_STAT_READY BIT(0) #define CORE_RC_STAT_READY BIT(0)
#define CORE_FABRIC_STAT 0x04000 #define CORE_FABRIC_STAT 0x04000
#define CORE_FABRIC_STAT_MASK 0x001F001F #define CORE_FABRIC_STAT_MASK 0x001F001F
#define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
#define CORE_LANE_CFG_REFCLK0REQ BIT(0) #define CORE_PHY_DEFAULT_BASE(port) (0x84000 + 0x4000 * (port))
#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
#define CORE_LANE_CFG_REFCLK0ACK BIT(2) #define PHY_LANE_CFG 0x00000
#define CORE_LANE_CFG_REFCLK1ACK BIT(3) #define PHY_LANE_CFG_REFCLK0REQ BIT(0)
#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10)) #define PHY_LANE_CFG_REFCLK1REQ BIT(1)
#define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port)) #define PHY_LANE_CFG_REFCLK0ACK BIT(2)
#define CORE_LANE_CTL_CFGACC BIT(15) #define PHY_LANE_CFG_REFCLK1ACK BIT(3)
#define PHY_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
#define PHY_LANE_CFG_REFCLKCGEN (BIT(30) | BIT(31))
#define PHY_LANE_CTL 0x00004
#define PHY_LANE_CTL_CFGACC BIT(15)
#define PORT_LTSSMCTL 0x00080 #define PORT_LTSSMCTL 0x00080
#define PORT_LTSSMCTL_START BIT(0) #define PORT_LTSSMCTL_START BIT(0)
@ -116,11 +120,32 @@
#define PORT_TUNSTAT_PERST_ACK_PEND BIT(1) #define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
#define PORT_PREFMEM_ENABLE 0x00994 #define PORT_PREFMEM_ENABLE 0x00994
struct reg_info {
u32 phy_lane_ctl;
u32 port_refclk;
u32 port_perst;
};
const struct reg_info t8103_hw = {
.phy_lane_ctl = PHY_LANE_CTL,
.port_refclk = PORT_REFCLK,
.port_perst = PORT_PERST,
};
#define PORT_T602X_PERST 0x082c
const struct reg_info t602x_hw = {
.phy_lane_ctl = 0,
.port_refclk = 0,
.port_perst = PORT_T602X_PERST,
};
struct apple_pcie_priv { struct apple_pcie_priv {
struct udevice *dev; struct udevice *dev;
void __iomem *base; void __iomem *base;
void __iomem *cfg_base; void __iomem *cfg_base;
struct list_head ports; struct list_head ports;
const struct reg_info *hw;
}; };
struct apple_pcie_port { struct apple_pcie_port {
@ -128,6 +153,7 @@ struct apple_pcie_port {
struct gpio_desc reset; struct gpio_desc reset;
ofnode np; ofnode np;
void __iomem *base; void __iomem *base;
void __iomem *phy;
struct list_head entry; struct list_head entry;
int idx; int idx;
}; };
@ -187,33 +213,32 @@ static int apple_pcie_setup_refclk(struct apple_pcie_priv *pcie,
u32 stat; u32 stat;
int res; int res;
res = readl_poll_sleep_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat, if (pcie->hw->phy_lane_ctl)
stat & CORE_RC_PHYIF_STAT_REFCLK, rmw_set(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
rmw_set(PHY_LANE_CFG_REFCLK0REQ, port->phy + PHY_LANE_CFG);
res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
stat, stat & PHY_LANE_CFG_REFCLK0ACK,
100, 50000); 100, 50000);
if (res < 0) if (res < 0)
return res; return res;
rmw_set(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx)); rmw_set(PHY_LANE_CFG_REFCLK1REQ, port->phy + PHY_LANE_CFG);
rmw_set(CORE_LANE_CFG_REFCLK0REQ, pcie->base + CORE_LANE_CFG(port->idx)); res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
stat, stat & PHY_LANE_CFG_REFCLK1ACK,
res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
stat, stat & CORE_LANE_CFG_REFCLK0ACK,
100, 50000);
if (res < 0)
return res;
rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
stat, stat & CORE_LANE_CFG_REFCLK1ACK,
100, 50000); 100, 50000);
if (res < 0) if (res < 0)
return res; return res;
rmw_clear(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx)); if (pcie->hw->phy_lane_ctl)
rmw_clear(PHY_LANE_CTL_CFGACC, port->phy + pcie->hw->phy_lane_ctl);
rmw_set(CORE_LANE_CFG_REFCLKEN, pcie->base + CORE_LANE_CFG(port->idx)); rmw_set(PHY_LANE_CFG_REFCLKEN, port->phy + PHY_LANE_CFG);
rmw_set(PORT_REFCLK_EN, port->base + PORT_REFCLK);
if (pcie->hw->port_refclk)
rmw_set(PORT_REFCLK_EN, port->base + pcie->hw->port_refclk);
return 0; return 0;
} }
@ -225,6 +250,7 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
fdt_addr_t addr; fdt_addr_t addr;
u32 stat, idx; u32 stat, idx;
int ret; int ret;
char name[16];
ret = gpio_request_by_name_nodev(np, "reset-gpios", 0, &reset, 0); ret = gpio_request_by_name_nodev(np, "reset-gpios", 0, &reset, 0);
if (ret) if (ret)
@ -244,11 +270,21 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
port->reset = reset; port->reset = reset;
port->np = np; port->np = np;
snprintf(name, sizeof(name), "port%d", port->idx);
addr = dev_read_addr_name(pcie->dev, name);
if (addr == FDT_ADDR_T_NONE)
addr = dev_read_addr_index(pcie->dev, port->idx + 2); addr = dev_read_addr_index(pcie->dev, port->idx + 2);
if (addr == FDT_ADDR_T_NONE) if (addr == FDT_ADDR_T_NONE)
return -EINVAL; return -EINVAL;
port->base = map_sysmem(addr, 0); port->base = map_sysmem(addr, 0);
snprintf(name, sizeof(name), "phy%d", port->idx);
addr = dev_read_addr_name(pcie->dev, name);
if (addr == FDT_ADDR_T_NONE)
port->phy = pcie->base + CORE_PHY_DEFAULT_BASE(port->idx);
else
port->phy = map_sysmem(addr, 0);
rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK); rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
/* Assert PERST# before setting up the clock */ /* Assert PERST# before setting up the clock */
@ -262,7 +298,7 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
udelay(100); udelay(100);
/* Deassert PERST# */ /* Deassert PERST# */
rmw_set(PORT_PERST_OFF, port->base + PORT_PERST); rmw_set(PORT_PERST_OFF, port->base + pcie->hw->port_perst);
dm_gpio_set_value(&reset, 0); dm_gpio_set_value(&reset, 0);
/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
@ -275,9 +311,6 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
return ret; return ret;
} }
rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK);
rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK);
list_add_tail(&port->entry, &pcie->ports); list_add_tail(&port->entry, &pcie->ports);
writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL); writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
@ -289,6 +322,12 @@ static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
readl_poll_sleep_timeout(port->base + PORT_LINKSTS, stat, readl_poll_sleep_timeout(port->base + PORT_LINKSTS, stat,
(stat & PORT_LINKSTS_UP), 100, 100000); (stat & PORT_LINKSTS_UP), 100, 100000);
if (pcie->hw->port_refclk)
rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK);
else
rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG);
rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK);
return 0; return 0;
} }
@ -299,6 +338,8 @@ static int apple_pcie_probe(struct udevice *dev)
ofnode of_port; ofnode of_port;
int i, ret; int i, ret;
pcie->hw = (struct reg_info *)dev_get_driver_data(dev);
pcie->dev = dev; pcie->dev = dev;
addr = dev_read_addr_index(dev, 0); addr = dev_read_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE) if (addr == FDT_ADDR_T_NONE)
@ -341,7 +382,8 @@ static int apple_pcie_remove(struct udevice *dev)
} }
static const struct udevice_id apple_pcie_of_match[] = { static const struct udevice_id apple_pcie_of_match[] = {
{ .compatible = "apple,pcie" }, { .compatible = "apple,t6020-pcie", .data = (ulong)&t602x_hw },
{ .compatible = "apple,pcie", .data = (ulong)&t8103_hw },
{ /* sentinel */ } { /* sentinel */ }
}; };