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ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP
The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
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03a7a82970
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3 changed files with 19 additions and 3 deletions
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@ -44,6 +44,10 @@
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#define I2C3_BASE_ADDR 0x30A40000
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#define I2C3_BASE_ADDR 0x30A40000
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#define I2C4_BASE_ADDR 0x30A50000
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#define I2C4_BASE_ADDR 0x30A50000
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#define UART4_BASE_ADDR 0x30A60000
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#define UART4_BASE_ADDR 0x30A60000
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#ifdef CONFIG_IMX8MP
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#define I2C5_BASE_ADDR 0x30AD0000
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#define I2C6_BASE_ADDR 0x30AE0000
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#endif
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#define USDHC1_BASE_ADDR 0x30B40000
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#define USDHC1_BASE_ADDR 0x30B40000
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#define USDHC2_BASE_ADDR 0x30B50000
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#define USDHC2_BASE_ADDR 0x30B50000
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#define QSPI0_AMBA_BASE 0x08000000
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#define QSPI0_AMBA_BASE 0x08000000
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@ -70,6 +70,12 @@ static void * const i2c_bases[] = {
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#ifdef I2C4_BASE_ADDR
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#ifdef I2C4_BASE_ADDR
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(void *)I2C4_BASE_ADDR,
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(void *)I2C4_BASE_ADDR,
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#endif
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#endif
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#ifdef I2C5_BASE_ADDR
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(void *)I2C5_BASE_ADDR,
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#endif
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#ifdef I2C6_BASE_ADDR
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(void *)I2C6_BASE_ADDR,
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#endif
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};
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};
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/* i2c_index can be from 0 - 3 */
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/* i2c_index can be from 0 - 3 */
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@ -36,11 +36,17 @@ void enable_ocotp_clk(unsigned char enable)
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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{
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/* 0 - 3 is valid i2c num */
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u8 i2c_ccgr[6] = {
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if (i2c_num > 3)
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CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
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#if (IS_ENABLED(CONFIG_IMX8MP))
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CCGR_I2C5_8MP, CCGR_I2C6_8MP
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#endif
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};
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if (i2c_num > ARRAY_SIZE(i2c_ccgr))
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return -EINVAL;
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return -EINVAL;
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clock_enable(CCGR_I2C1 + i2c_num, !!enable);
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clock_enable(i2c_ccgr[i2c_num], !!enable);
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return 0;
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return 0;
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}
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}
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