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Add a common get_ram_size() function and modify the the

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board-specific files to invoke that common implementation.
This commit is contained in:
wdenk 2004-01-06 22:38:14 +00:00
parent b299e41a0d
commit c83bf6a2d0
54 changed files with 1848 additions and 3374 deletions
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7
CHANGELOG
View file

@ -1,3 +1,10 @@
======================================================================
Changes since U-Boot 1.0.1:
======================================================================
* Add a common get_ram_size() function and modify the the
board-specific files to invoke that common implementation.
======================================================================
Changes for U-Boot 1.0.1:
======================================================================

101
board/LEOX/elpt860/elpt860.c
View file

@ -53,8 +53,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint init_sdram_table[] =
{
const uint init_sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
@ -90,8 +89,7 @@ const uint init_sdram_table[] =
0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
};
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
@ -147,8 +145,7 @@ const uint sdram_table[] =
/*
* Very early board init code (fpga boot, etc.)
*/
int
board_pre_init (void)
int board_pre_init (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
@ -159,7 +156,7 @@ board_pre_init (void)
immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
return ( 0 ); /* success */
return (0); /* success */
}
/*
@ -170,23 +167,21 @@ board_pre_init (void)
* Return 1 if no second DRAM bank, otherwise returns 0
*/
int
checkboard (void)
int checkboard (void)
{
unsigned char *s = getenv("serial#");
unsigned char *s = getenv ("serial#");
if ( !s || strncmp(s, "ELPT860", 7) )
if (!s || strncmp (s, "ELPT860", 7))
printf ("### No HW ID - assuming ELPT860\n");
return ( 0 ); /* success */
return (0); /* success */
}
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size_b0 = 0;
@ -194,8 +189,8 @@ initdram (int board_type)
/*
* This sequence initializes SDRAM chips on ELPT860 board
*/
upmconfig(UPMA, (uint *)init_sdram_table,
sizeof(init_sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) init_sdram_table,
sizeof (init_sdram_table) / sizeof (uint));
memctl->memc_mptpr = 0x0200;
memctl->memc_mamr = 0x18002111;
@ -203,8 +198,8 @@ initdram (int board_type)
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
upmconfig(UPMA, (uint *)sdram_table,
sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Preliminary prescaler for refresh (depends on number of
@ -258,8 +253,7 @@ initdram (int board_type)
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL,
(ulong *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
(ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
@ -267,16 +261,13 @@ initdram (int board_type)
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL,
(ulong *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
(ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if ( size8 < size9 ) /* leave configuration at 9 columns */
{
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
}
else /* back to 8 columns */
{
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay (500);
@ -289,8 +280,7 @@ initdram (int board_type)
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if ( size_b0 < 0x02000000 )
{
if (size_b0 < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay (1000);
@ -311,7 +301,7 @@ initdram (int board_type)
memctl->memc_mptpr = reg;
}
udelay(10000);
udelay (10000);
return (size_b0);
}
@ -327,54 +317,14 @@ initdram (int board_type)
*/
static long int
dram_size (long int mamr_value,
long int *base,
long int maxsize)
dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
{
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ( (val = *addr) != 0 )
{
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
{
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if ( val != (~cnt) )
{
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
@ -384,8 +334,7 @@ dram_size (long int mamr_value,
#define CFG_LBKs (CFG_PA2 | CFG_PA1)
void
reset_phy (void)
void reset_phy (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;

34
board/RPXClassic/RPXClassic.c
View file

@ -220,42 +220,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/*-----------------------------------------------------------------------------
* aschex_to_byte --

64
board/RPXlite/RPXlite.c
View file

@ -40,8 +40,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFCC25
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 00h in UPMA RAM)
*/
@ -97,22 +96,23 @@ const uint sdram_table[] =
int checkboard (void)
{
puts ("Board: RPXlite\n") ;
return (0) ;
puts ("Board: RPXlite\n");
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size10 ;
long int size10;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Refresh clock prescalar */
memctl->memc_mptpr = CFG_MPTPR ;
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mar = 0x00000000;
@ -122,12 +122,12 @@ long int initdram (int board_type)
memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002230 ; /* SDRAM bank 0 - refresh twice */
udelay(1);
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
@ -137,7 +137,8 @@ long int initdram (int board_type)
* try 10 column mode
*/
size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
return (size10);
}
@ -152,44 +153,13 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}

47
board/RRvision/RRvision.c
View file

@ -229,53 +229,8 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}

44
board/a3000/a3000.c
View file

@ -40,35 +40,16 @@ int checkboard (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -76,14 +57,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

52
board/atc/atc.c
View file

@ -269,13 +269,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val, size;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
ulong maxsize, size;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@ -325,54 +322,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size((long *)base, maxsize);
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(size - 1);
return (size);
}
}
return (maxsize);
}
int misc_init_r(void)

47
board/c2mon/c2mon.c
View file

@ -227,53 +227,8 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}

45
board/cpc45/cpc45.c
View file

@ -60,36 +60,16 @@ int checkboard(void)
long int initdram(int board_type)
{
int i, cnt;
volatile uchar * base = CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -97,14 +77,7 @@ long int initdram(int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

41
board/cpu86/cpu86.c
View file

@ -213,13 +213,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
ulong maxsize, size;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@ -269,41 +266,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size((long *)base, maxsize);
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
*orx_ptr = orx | ~(size - 1);
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
return (size);
}
long int initdram (int board_type)

44
board/cu824/cu824.c
View file

@ -47,35 +47,16 @@ int checkboard (void)
long int initdram(int board_type)
{
int i, cnt;
volatile uchar * base = CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -83,14 +64,7 @@ long int initdram(int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

107
board/esteem192e/esteem192e.c
View file

@ -30,14 +30,9 @@
/* ------------------------------------------------------------------------- */
static long int dram_size ( long int *base, long int maxsize);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*
@ -100,7 +95,7 @@ const uint sdram_table[] =
int checkboard (void)
{
puts ("Board: Esteem 192E\n");
return(0);
return (0);
}
/* ------------------------------------------------------------------------- */
@ -108,7 +103,7 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0, size_b1;
@ -118,9 +113,10 @@ long int initdram (int board_type)
memctl->memc_mptpr = 0x0200; /* divide by 32 */
memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL;*/ /* 0x18005112 TODO: explain here */
memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Map cs 2 and 3 to the SDRAM banks 0 and 1 at
@ -137,17 +133,12 @@ long int initdram (int board_type)
/* perform SDRAM initializsation sequence */
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
/* printf ("banks 0 and 1 are programed\n"); */
@ -156,23 +147,17 @@ long int initdram (int board_type)
* Check Bank 0 Memory Size for re-configuration
*
*/
size_b0 = get_ram_size ((ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
size_b1 = get_ram_size ((ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
size_b0 = dram_size ((ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
size_b1 = dram_size ((ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
printf ("\nbank 0 size %lu\nbank 1 size %lu\n",size_b0,size_b1);
printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
/* printf ("bank 1 size %u\n",size_b1); */
if(size_b1 == 0) {
if (size_b1 == 0) {
/*
* Adjust refresh rate if bank 0 isn't stuffed
*/
memctl->memc_mptpr = 0x0400; /* divide by 64 */
memctl->memc_br3 &= 0x0FFFFFFFE;
@ -180,12 +165,8 @@ long int initdram (int board_type)
* Adjust OR2 for size of bank 0
*/
memctl->memc_or2 |= 7 * size_b0;
}
else {
if(size_b0 < size_b1) {
} else {
if (size_b0 < size_b1) {
memctl->memc_br2 &= 0x00007FFE;
memctl->memc_br3 &= 0x00007FFF;
@ -198,15 +179,10 @@ long int initdram (int board_type)
* Adjust OR2 for size of bank 0
*/
memctl->memc_or2 |= 15 * size_b0;
memctl->memc_br2 += (size_b1 + 1);
}
else {
} else {
memctl->memc_br3 &= 0x00007FFE;
/*
* Adjust OR2 for size of bank 0
*/
@ -216,17 +192,13 @@ long int initdram (int board_type)
* Adjust OR3 for size of bank 1
*/
memctl->memc_or3 |= 15 * size_b1;
memctl->memc_br3 += (size_b0 + 1);
}
}
/* before leaving set all unused i/o pins to outputs */
/* before leaving set all unused i/o pins to outputs */
/*
/*
* --*Unused Pin List*--
*
* group/port bit number
@ -238,7 +210,7 @@ long int initdram (int board_type)
*
*/
/*
/*
* --*Pin Used for I/O List*--
*
* port input bit number output bit number either
@ -247,7 +219,6 @@ long int initdram (int board_type)
*
*/
immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
@ -261,56 +232,12 @@ long int initdram (int board_type)
immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high*/
immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */
immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size ( long int *base, long int maxsize)
{
volatile long int *addr;
long int cnt, val;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
}

50
board/etin/debris/debris.c
View file

@ -52,50 +52,28 @@ int checkflash (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
#if 0
long new_bank0_end;
long mear1;
long emear1;
#endif
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
#if 0
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);*/
mpc824x_mpc107_setreg(EMEAR1, emear1);
#endif
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

47
board/etx094/etx094.c
View file

@ -320,55 +320,10 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

43
board/fads/fads.c
View file

@ -186,45 +186,6 @@ static const uint edo_70ns[] =
#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
#endif
/* ------------------------------------------------------------------------- */
static long int dram_size (long int *base, long int maxsize)
{
volatile long int *addr=base;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
/* ------------------------------------------------------------------------- */
static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
{
@ -306,10 +267,10 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
/* if no dimm is inserted, noMbytes is still detected as 8m, so
* sanity check top and bottom of memory */
/* check bytes / 2 because dram_size tests at base+bytes, which
/* check bytes / 2 because get_ram_size tests at base+bytes, which
* is not mapped */
if (noMbytes == 8)
if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
return -1;
}

153
board/genietv/genietv.c
View file

@ -39,8 +39,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMB RAM)
*/
@ -103,14 +102,17 @@ int checkboard (void)
}
#if 0
static void PrintState(void)
static void PrintState (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &im->im_memctl;
printf("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, memctl->memc_or0);
printf("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, memctl->memc_or1);
printf("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, memctl->memc_or2);
printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
memctl->memc_or0);
printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
memctl->memc_or1);
printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
memctl->memc_or2);
}
#endif
@ -118,18 +120,18 @@ static void PrintState(void)
long int initdram (int board_type)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile immap_t *im = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &im->im_memctl;
long int size_b0, size_b1, size8;
/* Enable SDRAM */
/* Configuring PA7 for general purpouse output pin */
im->im_ioport.iop_papar &= ~CFG_PA7 ; /* 0 = general purpouse */
im->im_ioport.iop_padir |= CFG_PA7 ; /* 1 = output */
im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */
im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */
/* Enable SDRAM - PA7 = 1 */
im->im_ioport.iop_padat |= CFG_PA7 ; /* value of PA7 */
im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */
/*
* Preliminary prescaler for refresh (depends on number of
@ -137,11 +139,12 @@ long int initdram (int board_type)
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_4K ;
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
memctl->memc_mbmr = CFG_MBMR_8COL;
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMB, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
@ -150,10 +153,12 @@ long int initdram (int board_type)
*/
memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
memctl->memc_br1 =
((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
memctl->memc_br2 =
((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
/* perform SDRAM initialization sequence */
memctl->memc_mar = 0x00000088;
@ -163,7 +168,7 @@ long int initdram (int board_type)
memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
/* Execute refresh 8 times */
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
@ -179,15 +184,18 @@ long int initdram (int board_type)
*/
#if 0
PrintState();
PrintState ();
#endif
/* printf ("\nChecking bank1..."); */
size8 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
size_b0 = size8 ;
size_b0 = size8;
/* printf ("\nChecking bank2..."); */
size_b1 = dram_size (memctl->memc_mbmr, (ulong *)SDRAM_BASE2_PRELIM,SDRAM_MAX_SIZE);
size_b1 =
dram_size (memctl->memc_mbmr, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/*
* Final mapping: map bigger bank first
@ -196,17 +204,16 @@ long int initdram (int board_type)
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
if (size_b1 > 0)
{
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
memctl->memc_or2 =
((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
(size_b0 & BR_BA_MSK);
}
else
{
} else {
/*
* No bank 1
*
@ -218,17 +225,16 @@ long int initdram (int board_type)
}
/* If no memory detected, disable SDRAM */
if ((size_b0 + size_b1) == 0)
{
printf("disabling SDRAM!\n");
if ((size_b0 + size_b1) == 0) {
printf ("disabling SDRAM!\n");
/* Disable SDRAM - PA7 = 1 */
im->im_ioport.iop_padat &= ~CFG_PA7 ; /* value of PA7 */
im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */
}
/* else */
/* printf("done! (%08lx)\n", size_b0 + size_b1); */
#if 0
PrintState();
PrintState ();
#endif
return (size_b0 + size_b1);
}
@ -243,49 +249,31 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
static long int dram_size (long int mbmr_value, long int *base,
long int maxsize)
{
volatile long int *addr;
long int cnt, val;
long size;
/*memctl->memc_mbmr = mbmr_value; */
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
size = get_ram_size (base, maxsize);
*addr = ~cnt;
if (size) {
/* printf("(%08lx)", size); */
} else {
printf ("(0)");
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
printf("(0)");
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
/* printf("(%08lx)", cnt*sizeof(long)); */
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
return (0);
return (size);
}
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
#ifdef CFG_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR;
#endif
int pcmcia_init(void)
int pcmcia_init (void)
{
volatile pcmconf8xx_t *pcmp;
uint v, slota, slotb;
@ -293,7 +281,7 @@ int pcmcia_init(void)
/*
** Enable the PCMCIA for a Flash card.
*/
pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
#if 0
pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
@ -311,12 +299,11 @@ int pcmcia_init(void)
#endif
/* Check if any PCMCIA card is luged in. */
slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
if (!(slota || slotb))
{
printf("No card present\n");
if (!(slota || slotb)) {
printf ("No card present\n");
#ifdef PCMCIA_SLOT_A
pcmp->pcmc_pgcra = 0;
#endif
@ -324,50 +311,48 @@ int pcmcia_init(void)
pcmp->pcmc_pgcrb = 0;
#endif
return -1;
}
else
printf("Unknown card (");
} else
printf ("Unknown card (");
v = 0;
switch( (pcmp->pcmc_pipr >> 14) & 3 )
{
case 0x00 :
printf("5V");
switch ((pcmp->pcmc_pipr >> 14) & 3) {
case 0x00:
printf ("5V");
v = 5;
break;
case 0x01 :
printf("5V and 3V");
case 0x01:
printf ("5V and 3V");
v = 3;
break;
case 0x03 :
printf("5V, 3V and x.xV");
case 0x03:
printf ("5V, 3V and x.xV");
v = 3;
break;
}
switch(v){
switch (v) {
case 3:
printf("; using 3V");
printf ("; using 3V");
/* Enable 3 volt Vcc. */
break;
default:
printf("; unknown voltage");
printf ("; unknown voltage");
return -1;
}
printf(")\n");
printf (")\n");
/* disable pcmcia reset after a while */
udelay(20);
udelay (20);
pcmp->pcmc_pgcrb = 0;
/* If you using a real hd you should give a short
* spin-up time. */
#ifdef CONFIG_DISK_SPINUP_TIME
udelay(CONFIG_DISK_SPINUP_TIME);
udelay (CONFIG_DISK_SPINUP_TIME);
#endif
return 0;

34
board/hermes/hermes.c
View file

@ -225,42 +225,10 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

46
board/icecube/icecube.c
View file

@ -26,44 +26,6 @@
#include <pci.h>
#ifndef CFG_RAMBOOT
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@ -148,9 +110,9 @@ long int initdram (int board_type)
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
#endif
sdram_start(0);
test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
@ -163,9 +125,9 @@ long int initdram (int board_type)
#ifdef CONFIG_MPC5200_DDR
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
sdram_start(0);
test1 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
test2 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize2 = test1;

33
board/icu862/icu862.c
View file

@ -208,39 +208,8 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}

48
board/incaip/incaip.c
View file

@ -47,52 +47,6 @@ static ulong max_sdram_size(void)
return size;
}
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size(long int *base, long int maxsize)
{
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
long int initdram(int board_type)
{
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
@ -114,7 +68,7 @@ long int initdram(int board_type)
{
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
size = dram_size((ulong *)CFG_SDRAM_BASE,
size = get_ram_size((ulong *)CFG_SDRAM_BASE,
max_sdram_size());
if (size > max_size)

34
board/ip860/ip860.c
View file

@ -253,42 +253,10 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

42
board/iphase4539/iphase4539.c
View file

@ -198,9 +198,8 @@ long int initdram (int board_type)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *base;
volatile ulong *addr, cnt, val;
ulong save[32]; /* to make test non-destructive */
int i, maxsize;
ulong maxsize;
int i;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
@ -237,43 +236,10 @@ long int initdram (int board_type)
*/
maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
maxsize = get_ram_size((long *)base, maxsize);
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
memctl->memc_or1 |= ~(maxsize - 1);
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
memctl->memc_or1 |= ~(cnt * sizeof (long) - 1);
maxsize = cnt * sizeof (long) / 2;
break;
}
}
maxsize *= 2;
if (maxsize != hwc_main_sdram_size ())
printf ("Oops: memory test has not found all memory!\n");
#endif

100
board/ivm/ivm.c
View file

@ -41,8 +41,7 @@ static long int dram_size (long int, long int *, long int);
/*
* 50 MHz SHARC access using UPM A
*/
const uint sharc_table[] =
{
const uint sharc_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -89,8 +88,7 @@ const uint sharc_table[] =
/*
* 50 MHz SDRAM access using UPM B
*/
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -161,19 +159,18 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
long int initdram (int board_type)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0;
/* enable SDRAM clock ("switch on" SDRAM) */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE ; /* output */
immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */
udelay(1);
immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */
immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
udelay (1);
/*
* Map controller bank 1 for ELIC SACCO
@ -190,7 +187,8 @@ initdram (int board_type)
/*
* Configure UPMA for SHARC
*/
upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sharc_table,
sizeof (sharc_table) / sizeof (uint));
#if defined(CONFIG_IVML24)
/*
@ -211,7 +209,8 @@ initdram (int board_type)
/*
* Configure UPMB for SDRAM
*/
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMB, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
@ -225,25 +224,25 @@ initdram (int board_type)
memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
udelay(200);
udelay (200);
memctl->memc_mcr = 0x80806105; /* precharge */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806106; /* load mode register */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
@ -251,7 +250,9 @@ initdram (int board_type)
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
size_b0 =
dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
@ -268,60 +269,29 @@ initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mbmr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
void reset_phy(void)
void reset_phy (void)
{
immap_t *immr = (immap_t *)CFG_IMMR;
immap_t *immr = (immap_t *) CFG_IMMR;
/* De-assert Ethernet Powerdown */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN ; /* output */
immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */
immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay(1000);
udelay (1000);
/*
* RESET is implemented by a positive pulse of at least 1 us
@ -353,16 +323,16 @@ void show_boot_progress (int status)
# endif /* STATUS_LED_YELLOW */
# if defined(STATUS_LED_BOOT)
if (status == 6)
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
}
/* ------------------------------------------------------------------------- */
void ide_set_reset(int on)
void ide_set_reset (int on)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Configure PC for IDE Reset Pin

34
board/kup4k/kup4k.c
View file

@ -230,42 +230,10 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return(get_ram_size(base, maxsize));
}
#endif

84
board/lantec/lantec.c
View file

@ -39,8 +39,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
@ -104,7 +103,7 @@ const uint sdram_table[] =
int checkboard (void)
{
printf("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
return 0;
}
@ -112,7 +111,7 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0;
int i;
@ -120,9 +119,10 @@ long int initdram (int board_type)
/*
* Configure UPMA for SDRAM
*/
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */;
memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
/* burst length=4, burst type=sequential, CAS latency=2 */
memctl->memc_mar = 0x00000088;
@ -137,26 +137,30 @@ long int initdram (int board_type)
memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
/* mode initialization (offset 5) */
udelay(200); /* 0x80006105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
udelay (200); /* 0x80006105 */
memctl->memc_mcr =
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
udelay(1); /* 0x80006130 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
udelay(1); /* 0x80006130 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
udelay (1); /* 0x80006130 */
memctl->memc_mcr =
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
udelay (1); /* 0x80006130 */
memctl->memc_mcr =
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
udelay(1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
udelay (1); /* 0x80006106 */
memctl->memc_mcr =
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
udelay(200);
udelay (200);
/* Need at least 10 DRAM accesses to stabilize */
for (i=0; i<10; ++i) {
volatile unsigned long *addr = \
(volatile unsigned long *)SDRAM_BASE3_PRELIM;
for (i = 0; i < 10; ++i) {
volatile unsigned long *addr =
(volatile unsigned long *) SDRAM_BASE3_PRELIM;
unsigned long val;
val = *(addr + i);
@ -167,8 +171,7 @@ long int initdram (int board_type)
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MAMR_8COL,
(ulong *)SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
(ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
@ -178,7 +181,7 @@ long int initdram (int board_type)
memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
udelay(1000);
udelay (1000);
return (size_b0);
}
@ -193,44 +196,13 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}

34
board/lwmon/lwmon.c
View file

@ -326,42 +326,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

44
board/musenki/musenki.c
View file

@ -47,35 +47,16 @@ int checkflash (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -83,14 +64,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

55
board/mvblue/mvblue.c
View file

@ -77,53 +77,24 @@ int checkboard (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;
volatile ulong *addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
cnt >>= 1) {
addr = (volatile ulong *) base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof (long) - 1;
ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >>
MICR_ADDR_SHIFT);
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >>
MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg (MEAR1, mear1);
mpc824x_mpc107_setreg (EMEAR1, emear1);
ret = cnt * sizeof (long);
goto Done;
}
}
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/* ------------------------------------------------------------------------- */

29
board/mvs1/mvs1.c
View file

@ -337,37 +337,10 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1;; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
/* NOTREACHED */
return (get_ram_size(base, maxsize));
}

234
board/nx823/nx823.c
View file

@ -36,16 +36,12 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
const uint sdram_table[] = {
#if (MPC8XX_SPEED <= 50000000L)
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0F07EC04,
0x01BBD804,
0x1FF7F440,
0xFFFFFC07,
0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
0xFFFFFFFF,
/*
@ -56,95 +52,47 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
0x1FE7F434,
0xEFABE834,
0x1FA7D435,
0x1FE7F434, 0xEFABE834, 0x1FA7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x0F07EC04,
0x10EFDC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xFFAFFC40,
0xFFAFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0E07E804,
0x01BBD000,
0x1FF7F447,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x0E07E800,
0x10EFD400,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC47,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF7DC84,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF
0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
#else
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFEC04,
0x11AFDC04,
0xEFBBF800,
0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
0x1FF7F447,
/*
@ -155,55 +103,35 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
0x1FF7F434,
0xEFEBE834,
0x1FB7D435,
0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFEC04,
0x10AFDC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xEFBBF800,
0x1FF7F447,
0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFE800,
0x01BBD004,
0x1FF7F447,
0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFE800,
0x10AFD400,
0xF0AFFC00,
0xF0AFFC00,
0xE1BBF804,
0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF7DC84,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07,
0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
@ -233,11 +161,12 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0, size_b1, size8, size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Up to 2 Banks of 64Mbit x 2 devices
@ -252,7 +181,7 @@ long int initdram (int board_type)
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
udelay (200);
/*
* Map controller SDRAM bank 1
@ -264,14 +193,14 @@ long int initdram (int board_type)
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
udelay(1);
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
@ -292,14 +221,16 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
@ -307,7 +238,7 @@ long int initdram (int board_type)
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay(500);
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
@ -317,7 +248,7 @@ long int initdram (int board_type)
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE2_PRELIM,
size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
@ -330,7 +261,7 @@ long int initdram (int board_type)
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay(1000);
udelay (1000);
}
/*
@ -338,18 +269,25 @@ long int initdram (int board_type)
*/
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
memctl->memc_or2 =
((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
memctl->memc_or1 =
((-size_b0) & 0xFFFF0000) |
CFG_OR_TIMING_SDRAM;
memctl->memc_br1 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
BR_V)
+ size_b1;
} else {
unsigned long reg;
/*
* No bank 0
*
@ -365,18 +303,25 @@ long int initdram (int board_type)
} else { /* SDRAM Bank 0 is bigger - map first */
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
memctl->memc_or1 =
((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 =
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
memctl->memc_or2 =
((-size_b1) & 0xFFFF0000) |
CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
BR_V)
+ size_b0;
} else {
unsigned long reg;
/*
* No bank 1
*
@ -391,7 +336,7 @@ long int initdram (int board_type)
}
}
udelay(10000);
udelay (10000);
return (size_b0 + size_b1);
}
@ -406,40 +351,15 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
return (get_ram_size (base, maxsize));
}
u_long *my_sernum;
@ -452,16 +372,16 @@ int misc_init_r (void)
u_char *e = gd->bd->bi_enetaddr;
/* save serial numbre from flash (uniquely programmed) */
my_sernum = malloc(8);
memcpy(my_sernum,gd->bd->bi_sernum,8);
my_sernum = malloc (8);
memcpy (my_sernum, gd->bd->bi_sernum, 8);
/* save env variables according to sernum */
sprintf(tmp,"%08lx%08lx",my_sernum[0],my_sernum[1]);
setenv("serial#",tmp);
sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
setenv ("serial#", tmp);
sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
,e[0],e[1],e[2],e[3],e[4],e[5]);
setenv("ethaddr",tmp);
sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
e[4], e[5]);
setenv ("ethaddr", tmp);
return (0);
}
@ -470,7 +390,7 @@ void load_sernum_ethaddr (void)
DECLARE_GLOBAL_DATA_PTR;
int i;
bd_t * bd = gd->bd;
bd_t *bd = gd->bd;
for (i = 0; i < 8; i++) {
bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);

44
board/oxc/oxc.c
View file

@ -35,35 +35,16 @@ int checkboard (void)
long int initdram (int board_type)
{
#ifndef CFG_RAMBOOT
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -71,14 +52,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
#else
/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
return (16 << 20);

41
board/pm826/pm826.c
View file

@ -221,13 +221,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
volatile ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
ulong maxsize, size;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@ -274,41 +271,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size((long *)base, maxsize);
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
*orx_ptr = orx | ~(size - 1);
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
return (size);
}

47
board/pn62/pn62.c
View file

@ -76,39 +76,18 @@ int checkboard (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;
volatile ulong *addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
show_startup_phase (2);
for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
cnt >>= 1) {
addr = (volatile ulong *) base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof (long) - 1;
ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg (MEAR1);
emear1 = mpc824x_mpc107_getreg (EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -116,15 +95,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg (MEAR1, mear1);
mpc824x_mpc107_setreg (EMEAR1, emear1);
ret = cnt * sizeof (long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
show_startup_phase (3);
return ret;
return (size);
}
/*

33
board/r360mpi/r360mpi.c
View file

@ -258,41 +258,10 @@ static long int dram_size (long int mamr_value,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

78
board/rbc823/rbc823.c
View file

@ -127,14 +127,14 @@ const uint static_table[] =
int checkboard (void)
{
unsigned char *s = getenv("serial#");
unsigned char *s = getenv ("serial#");
if (!s || strncmp(s, "TQM8", 4)) {
if (!s || strncmp (s, "TQM8", 4)) {
printf ("### No HW ID - assuming RBC823\n");
return (0);
}
puts(s);
puts (s);
putc ('\n');
return (0);
@ -144,11 +144,12 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0, size8, size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* 1 Bank of 64Mbit x 2 devices
@ -162,19 +163,19 @@ long int initdram (int board_type)
memctl->memc_or4 = CFG_OR4_PRELIM;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
udelay (200);
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
udelay(1);
udelay (1);
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
udelay(200);
udelay (200);
memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
udelay(1);
udelay (1);
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
udelay(200);
udelay (200);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
@ -192,13 +193,15 @@ long int initdram (int board_type)
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
@ -206,7 +209,7 @@ long int initdram (int board_type)
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay(500);
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
@ -216,10 +219,10 @@ long int initdram (int board_type)
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if ((size_b0 < 0x02000000) ) {
if ((size_b0 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay(1000);
udelay (1000);
}
/* SDRAM Bank 0 is bigger - map first */
@ -227,7 +230,7 @@ long int initdram (int board_type)
memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
udelay(10000);
udelay (10000);
return (size_b0);
}
@ -242,50 +245,25 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return cnt * sizeof(long);
/* NOTREACHED */
return (get_ram_size (base, maxsize));
}
void doc_init(void)
void doc_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
upmconfig (UPMB, (uint *) static_table,
sizeof (static_table) / sizeof (uint));
memctl->memc_mbmr = MAMR_DSA_1_CYCL;
doc_probe(FLASH_BASE1_PRELIM);
doc_probe (FLASH_BASE1_PRELIM);
}

47
board/rmu/rmu.c
View file

@ -155,53 +155,8 @@ static long int dram_size (long int mamr_value, long int *base,
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}

44
board/sandpoint/sandpoint.c
View file

@ -52,35 +52,16 @@ int checkflash (void)
long int initdram (int board_type)
{
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -88,14 +69,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
}
/*

34
board/siemens/CCM/ccm.c
View file

@ -333,42 +333,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

99
board/siemens/IAD210/IAD210.c
View file

@ -41,8 +41,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
@ -103,13 +102,14 @@ const uint sdram_table[] =
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile iop8xx_t *iop = &immap->im_ioport;
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
long int size;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Preliminary prescaler for refresh (depends on number of
@ -131,21 +131,21 @@ long int initdram (int board_type)
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
udelay(1);
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
@ -155,7 +155,8 @@ long int initdram (int board_type)
* Check Bank 0 Memory Size for re-configuration
*
*/
size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
@ -169,11 +170,11 @@ long int initdram (int board_type)
memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
udelay(10000);
udelay (10000);
/* prepare pin multiplexing for fast ethernet */
atmLoad();
atmLoad ();
fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
@ -191,46 +192,15 @@ long int initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}
/*
@ -242,25 +212,25 @@ int checkboard (void)
return (0);
}
void board_serial_init(void)
void board_serial_init (void)
{
;/* nothing to do here */
; /* nothing to do here */
}
void board_ether_init(void)
void board_ether_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile iop8xx_t *iop = &immap->im_ioport;
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
atmLoad();
atmLoad ();
fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
}
int board_pre_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile iop8xx_t *iop = &immap->im_ioport;
@ -288,30 +258,29 @@ int board_pre_init (void)
return 0;
}
void board_get_enetaddr (uchar *addr)
void board_get_enetaddr (uchar * addr)
{
int i;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile cpm8xx_t *cpm = &immap->im_cpm;
unsigned int rccrtmp;
char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
for (i=0; i<6; i++)
for (i = 0; i < 6; i++)
addr[i] = default_mac_addr[i];
printf("There is an error in the i2c driver .. /n");
printf("You need to fix it first....../n");
printf ("There is an error in the i2c driver .. /n");
printf ("You need to fix it first....../n");
rccrtmp = cpm->cp_rccr;
cpm->cp_rccr |= 0x0020;
i2c_reg_read(0xa0, 0);
i2c_reg_read (0xa0, 0);
printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
cpm->cp_rccr = rccrtmp;
}

41
board/siemens/SCM/scm.c
View file

@ -235,13 +235,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
ulong maxsize, size;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@ -291,41 +288,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size((long *)base, maxsize);
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
*orx_ptr = orx | ~(size - 1);
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
return (size);
}
/*

141
board/siemens/pcu_e/pcu_e.c
View file

@ -42,8 +42,7 @@ static void puma_load (ulong addr, ulong len);
/*
* 50 MHz SDRAM access using UPM A
*/
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -98,8 +97,7 @@ const uint sdram_table[] =
/*
* PUMA access using UPM B
*/
const uint puma_table[] =
{
const uint puma_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -158,10 +156,9 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
long int initdram (int board_type)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0, reg;
int i;
@ -169,7 +166,8 @@ initdram (int board_type)
/*
* Configure UPMA for SDRAM
*/
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = CFG_MPTPR;
@ -192,28 +190,28 @@ initdram (int board_type)
/* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(200); /* 0x8000A105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
udelay (200); /* 0x8000A105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
#else /* XXX */
udelay(200); /* 0x80004105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
udelay (200); /* 0x80004105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
#endif /* XXX */
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
udelay (1); /* 0x8000A830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
#else /* XXX */
udelay(1); /* 0x80004830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
udelay (1); /* 0x80004830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
#endif /* XXX */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
udelay (1); /* 0x8000A106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
#else /* XXX */
udelay(1); /* 0x80004106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
udelay (1); /* 0x80004106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
#endif /* XXX */
reg = memctl->memc_mamr;
@ -222,14 +220,16 @@ initdram (int board_type)
reg |= MAMR_PTAE; /* enable refresh */
memctl->memc_mamr = reg;
udelay(200);
udelay (200);
/* Need at least 10 DRAM accesses to stabilize */
for (i=0; i<10; ++i) {
for (i = 0; i < 10; ++i) {
#if PCU_E_WITH_SWAPPED_CS /* XXX */
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
volatile unsigned long *addr =
(volatile unsigned long *) SDRAM_BASE5_PRELIM;
#else /* XXX */
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
volatile unsigned long *addr =
(volatile unsigned long *) SDRAM_BASE2_PRELIM;
#endif /* XXX */
unsigned long val;
@ -241,9 +241,9 @@ initdram (int board_type)
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
@ -259,12 +259,13 @@ initdram (int board_type)
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#endif /* XXX */
udelay(1000);
udelay (1000);
/*
* Configure UPMB for PUMA
*/
upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
upmconfig (UPMB, (uint *) puma_table,
sizeof (puma_table) / sizeof (uint));
return (size_b0);
}
@ -279,46 +280,15 @@ initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
@ -332,9 +302,9 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
void reset_phy(void)
void reset_phy (void)
{
immap_t *immr = (immap_t *)CFG_IMMR;
immap_t *immr = (immap_t *) CFG_IMMR;
ulong value;
/* Configure all needed port pins for GPIO */
@ -403,23 +373,23 @@ void reset_phy(void)
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr, len;
switch (argc) {
case 2: /* PUMA reset */
if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
puma_status ();
return 0;
}
break;
case 4: /* PUMA load addr len */
if (strcmp(argv[1],"load") != 0)
if (strcmp (argv[1], "load") != 0)
break;
addr = simple_strtoul(argv[2], NULL, 16);
len = simple_strtoul(argv[3], NULL, 16);
addr = simple_strtoul (argv[2], NULL, 16);
len = simple_strtoul (argv[3], NULL, 16);
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
addr, len, len);
@ -432,12 +402,11 @@ int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
puma, 4, 1, do_puma,
U_BOOT_CMD (puma, 4, 1, do_puma,
"puma - access PUMA FPGA\n",
"status - print PUMA status\n"
"puma load addr len - load PUMA configuration data\n"
);
"puma load addr len - load PUMA configuration data\n");
#endif /* CFG_CMD_BSP */
@ -445,7 +414,7 @@ U_BOOT_CMD(
static void puma_set_mode (int mode)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* disable PUMA in memory controller */
@ -483,9 +452,9 @@ static void puma_set_mode (int mode)
static void puma_load (ulong addr, ulong len)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
uchar *data = (uchar *)addr;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
uchar *data = (uchar *) addr;
int i;
/* align length */
@ -517,7 +486,7 @@ static void puma_load (ulong addr, ulong len)
#endif /* XXX */
/* wait until INIT indicates completion of reset */
for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
udelay (1000);
if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
break;
@ -543,14 +512,14 @@ static void puma_status (void)
{
/* Check state */
printf ("PUMA initialization is %scomplete\n",
puma_init_done() ? "" : "NOT ");
puma_init_done ()? "" : "NOT ");
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static int puma_init_done (void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/* make sure pin is GPIO input */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
@ -569,16 +538,16 @@ int misc_init_r (void)
char *s;
printf ("PUMA: ");
if (puma_init_done()) {
if (puma_init_done ()) {
printf ("initialized\n");
return 0;
}
if ((s = getenv("puma_addr")) != NULL)
addr = simple_strtoul(s, NULL, 16);
if ((s = getenv ("puma_addr")) != NULL)
addr = simple_strtoul (s, NULL, 16);
if ((s = getenv("puma_len")) != NULL)
len = simple_strtoul(s, NULL, 16);
if ((s = getenv ("puma_len")) != NULL)
len = simple_strtoul (s, NULL, 16);
if ((!addr) || (!len)) {
printf ("net list undefined\n");

44
board/sl8245/sl8245.c
View file

@ -37,35 +37,16 @@ int checkboard (void)
long int initdram (int board_type)
{
#ifndef CFG_RAMBOOT
int i, cnt;
volatile uchar * base= CFG_SDRAM_BASE;
volatile ulong * addr;
ulong save[32];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -73,14 +54,7 @@ long int initdram (int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
#else
return CFG_MAX_RAM_SIZE;
#endif

26
board/snmc/qs850/qs850.c
View file

@ -222,32 +222,8 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
return (get_ram_size(base, maxsize));
}

25
board/snmc/qs860t/qs860t.c
View file

@ -229,31 +229,8 @@ static long int dram_size (long int mbmr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mbmr = mbmr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
return (get_ram_size(base, maxsize));
}

76
board/spd8xx/spd8xx.c
View file

@ -34,8 +34,7 @@ static long int dram_size (long int, long int *, long int);
#define _NOT_USED_ 0xFFFFFFFF
const uint sharc_table[] =
{
const uint sharc_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -79,8 +78,7 @@ const uint sharc_table[] =
};
const uint sdram_table[] =
{
const uint sdram_table[] = {
/*
* Single Read. (Offset 0 in UPM RAM)
*/
@ -145,10 +143,9 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0;
@ -168,7 +165,8 @@ initdram (int board_type)
#if 0
/* Configure SHARC at UMA */
upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sharc_table,
sizeof (sharc_table) / sizeof (uint));
/* Map controller bank 5 to the SHARC */
memctl->memc_or5 = CFG_OR5;
memctl->memc_br5 = CFG_BR5;
@ -177,7 +175,8 @@ initdram (int board_type)
memctl->memc_mamr = 0x00001000;
/* Configure SDRAM at UMB */
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMB, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
@ -191,13 +190,13 @@ initdram (int board_type)
memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
udelay(200);
udelay (200);
memctl->memc_mcr = 0x80806105;
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130;
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806130;
udelay(1);
udelay (1);
memctl->memc_mcr = 0x80806106;
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
@ -205,7 +204,9 @@ initdram (int board_type)
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
size_b0 =
dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
@ -222,53 +223,22 @@ initdram (int board_type)
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mbmr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
return (get_ram_size (base, maxsize));
}
/* ------------------------------------------------------------------------- */
void reset_phy(void)
void reset_phy (void)
{
immap_t *immr = (immap_t *)CFG_IMMR;
immap_t *immr = (immap_t *) CFG_IMMR;
ushort sreg;
/* Configure extra port pins for NS DP83843 PHY */
@ -302,9 +272,9 @@ void reset_phy(void)
/* ------------------------------------------------------------------------- */
void ide_set_reset(int on)
void ide_set_reset (int on)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
/*
* Configure PC for IDE Reset Pin

51
board/tqm8260/tqm8260.c
View file

@ -224,13 +224,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize, size;
int i;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
@ -280,52 +277,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function. */
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
size = cnt * sizeof (long);
/* Restore the original data before leaving the function. */
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
/* Write the actual size to ORx
*/
size = get_ram_size((long *)base, maxsize);
*orx_ptr = orx | ~(size - 1);
return (size);
}
}
return (maxsize);
}
long int initdram (int board_type)

47
board/tqm8xx/tqm8xx.c
View file

@ -398,55 +398,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val, size;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
size = cnt * sizeof (long);
/* Restore the original data before returning
*/
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
return (get_ram_size(base, maxsize));
}
/* ------------------------------------------------------------------------- */

48
board/utx8245/utx8245.c
View file

@ -49,11 +49,10 @@ int checkboard(void)
long int initdram(int board_type)
{
#if 1
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;
volatile ulong *addr;
ulong save[SAVE_SZ];
ulong val, ret = 0;
long size;
long new_bank0_end;
long mear1;
long emear1;
/*
write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
@ -61,33 +60,11 @@ long int initdram(int board_type)
write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
*/
for (i=0; i<SAVE_SZ; i++) {
save[i] = 0; /* clear table */
}
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
addr = (volatile ulong *)base + cnt;
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *)base;
save[i] = *addr;
*addr = 0;
if (*addr != 0) {
*addr = save[i];
goto Done;
}
for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
addr = (volatile ulong *)base + cnt;
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
ulong new_bank0_end = cnt * sizeof(long) - 1;
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
new_bank0_end = size - 1;
mear1 = mpc824x_mpc107_getreg(MEAR1);
emear1 = mpc824x_mpc107_getreg(EMEAR1);
mear1 = (mear1 & 0xFFFFFF00) |
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
emear1 = (emear1 & 0xFFFFFF00) |
@ -95,14 +72,7 @@ long int initdram(int board_type)
mpc824x_mpc107_setreg(MEAR1, mear1);
mpc824x_mpc107_setreg(EMEAR1, emear1);
ret = cnt * sizeof(long);
goto Done;
}
}
ret = CFG_MAX_RAM_SIZE;
Done:
return ret;
return (size);
#else
return (CFG_MAX_RAM_SIZE);
#endif

131
board/w7o/w7o.c
View file

@ -30,7 +30,7 @@
#include "errors.h"
#include <watchdog.h>
unsigned long get_dram_size(void);
unsigned long get_dram_size (void);
/*
* Macros to transform values
@ -47,9 +47,9 @@ int board_pre_init (void)
/*
* Setup GPIO pins - reset devices.
*/
out32(IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
out32(IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
out32(IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@ -63,24 +63,24 @@ int board_pre_init (void)
* IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
* IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,
INT0 highest priority*/
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#elif defined(CONFIG_W7OLMC)
/*
* Setup GPIO pins
*/
out32(IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
out32(IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
out32(IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@ -94,27 +94,27 @@ int board_pre_init (void)
* IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
* IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,
INT0 highest priority*/
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,
INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#else /* Unknown */
# error "Unknown W7O board configuration"
#endif
WATCHDOG_RESET(); /* Reset the watchdog */
temp_uart_init(); /* init the uart for debug */
WATCHDOG_RESET(); /* Reset the watchdog */
test_led(); /* test the LEDs */
test_sdram(get_dram_size()); /* test the dram */
log_stat(ERR_POST1); /* log status,post1 complete */
WATCHDOG_RESET (); /* Reset the watchdog */
temp_uart_init (); /* init the uart for debug */
WATCHDOG_RESET (); /* Reset the watchdog */
test_led (); /* test the LEDs */
test_sdram (get_dram_size ()); /* test the dram */
log_stat (ERR_POST1); /* log status,post1 complete */
return 0;
}
@ -131,17 +131,16 @@ int checkboard (void)
puts ("Board: ");
/* VPD data present in I2C EEPROM */
if (vpd_get_data(CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
/*
* Known board type.
*/
if (vpd.productId[0] &&
((strncmp(vpd.productId, "GMM", 3) == 0) ||
(strncmp(vpd.productId, "CMM", 3) == 0))) {
((strncmp (vpd.productId, "GMM", 3) == 0) ||
(strncmp (vpd.productId, "CMM", 3) == 0))) {
/* Output board information on startup */
printf("\"%s\", revision '%c', serial# %ld, manufacturer %u\n",
vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
return (0);
}
}
@ -154,7 +153,7 @@ int checkboard (void)
long int initdram (int board_type)
{
return get_dram_size();
return get_dram_size ();
}
unsigned long get_dram_size (void)
@ -163,20 +162,20 @@ unsigned long get_dram_size (void)
int size = 0;
/* Get bank Size registers */
mtdcr(memcfga, mem_mb0cf); /* get bank 0 config reg */
regs[0] = mfdcr(memcfgd);
mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */
regs[0] = mfdcr (memcfgd);
mtdcr(memcfga, mem_mb1cf); /* get bank 1 config reg */
regs[1] = mfdcr(memcfgd);
mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */
regs[1] = mfdcr (memcfgd);
mtdcr(memcfga, mem_mb2cf); /* get bank 2 config reg */
regs[2] = mfdcr(memcfgd);
mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */
regs[2] = mfdcr (memcfgd);
mtdcr(memcfga, mem_mb3cf); /* get bank 3 config reg */
regs[3] = mfdcr(memcfgd);
mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */
regs[3] = mfdcr (memcfgd);
/* compute the size, add each bank if enabled */
for(i = 0; i < 4; i++) {
for (i = 0; i < 4; i++) {
if (regs[i] & 0x0001) { /* if enabled, */
tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
@ -192,39 +191,41 @@ int misc_init_f (void)
return 0;
}
static void
w7o_env_init(VPD *vpd)
static void w7o_env_init (VPD * vpd)
{
/*
* Read VPD
*/
if (vpd_get_data(CFG_DEF_EEPROM_ADDR, vpd) != 0)
if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0)
return;
/*
* Known board type.
*/
if (vpd->productId[0] &&
((strncmp(vpd->productId, "GMM", 3) == 0) ||
(strncmp(vpd->productId, "CMM", 3) == 0))) {
((strncmp (vpd->productId, "GMM", 3) == 0) ||
(strncmp (vpd->productId, "CMM", 3) == 0))) {
char buf[30];
char *eth;
unsigned char *serial = getenv("serial#");
unsigned char *ethaddr = getenv("ethaddr");
unsigned char *serial = getenv ("serial#");
unsigned char *ethaddr = getenv ("ethaddr");
/* Set 'serial#' envvar if serial# isn't set */
if (!serial) {
sprintf(buf, "%s-%ld", vpd->productId, vpd->serialNum);
setenv("serial#", buf);
sprintf (buf, "%s-%ld", vpd->productId,
vpd->serialNum);
setenv ("serial#", buf);
}
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
eth = vpd->ethAddrs[0];
if (ethaddr && (strcmp(ethaddr, MK_STR(CONFIG_ETHADDR)) == 0)) {
if (ethaddr
&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eth[0], eth[1], eth[2], eth[3], eth[4], eth[5]);
setenv("ethaddr", buf);
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eth[0], eth[1], eth[2], eth[3], eth[4],
eth[5]);
setenv ("ethaddr", buf);
}
}
} /* w7o_env_init() */
@ -237,35 +238,35 @@ int misc_init_r (void)
#if defined(CONFIG_W7OLMG)
unsigned long greg; /* GPIO Register */
greg = in32(IBM405GP_GPIO0_OR);
greg = in32 (IBM405GP_GPIO0_OR);
/*
* XXX - Unreset devices - this should be moved into VxWorks driver code
*/
greg |= 0x41800000L; /* SAM, PHY, Galileo */
out32(IBM405GP_GPIO0_OR, greg); /* set output pins to default */
out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */
#endif /* CONFIG_W7OLMG */
/*
* Initialize W7O environment variables
*/
w7o_env_init(&vpd);
w7o_env_init (&vpd);
/*
* Initialize the FPGA(s).
*/
if (init_fpga() == 0)
test_fpga((unsigned short *)CONFIG_FPGAS_BASE);
if (init_fpga () == 0)
test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
/* More POST testing. */
post2();
post2 ();
/* Done with hardware initialization and POST. */
log_stat(ERR_POSTOK);
log_stat (ERR_POSTOK);
/* Call silly, fail safe boot init routine */
init_fsboot();
init_fsboot ();
return (0);
}

2
common/Makefile
View file

@ -47,7 +47,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o \
hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \
s_record.o soft_i2c.o soft_spi.o spartan2.o \
usb.o usb_kbd.o usb_storage.o \
virtex2.o xilinx.o
virtex2.o xilinx.o memsize.o
OBJS = $(AOBJS) $(COBJS)

77
common/memsize.c Normal file
View file

@ -0,0 +1,77 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'.
*/
long get_ram_size(volatile long *base, long maxsize)
{
volatile long *addr;
long save[32];
long cnt;
long val;
long size;
int i = 0;
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function.
*/
*addr = save[i];
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
*addr = save[--i];
}
return (0);
}
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
size = cnt * sizeof (long);
/* Restore the original data before leaving the function.
*/
for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt;
*addr = save[--i];
}
return (size);
}
}
return (maxsize);
}

3
include/common.h
View file

@ -219,6 +219,9 @@ int misc_init_r (void);
/* common/exports.c */
void jumptable_init(void);
/* common/memsize.c */
int get_ram_size (volatile long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void fdc_hw_init (void);

6
include/exports.h
View file

@ -1,5 +1,5 @@
#ifndef __MON_SYS_CALL_H__
#define __MON_SYS_CALL_H__
#ifndef __EXPORTS_H__
#define __EXPORTS_H__
#ifndef __ASSEMBLY__
@ -43,4 +43,4 @@ enum {
extern gd_t *global_data;
#endif
#endif
#endif /* __EXPORTS_H__ */

2
include/version.h
View file

@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
#define U_BOOT_VERSION "U-Boot 1.0.1"
#define U_BOOT_VERSION "U-Boot 1.0.2"
#endif /* __VERSION_H__ */