board: mediatek: add MT7987 reference boards

This patch adds general board files based on MT7987 SoC.

MT7987 uses one mmc controller for booting from both SD and eMMC, and the
pins of mmc controller are also shared with one spi controller.
So three configs are need for these boot types:

1. mt7987_rfb_defconfig - SPI-NOR (spi2) and SPI-NAND (spi0)
2. mt7987_emmc_rfb_defconfig - eMMC + SPI-NOR (spi2)
3. mt7987_sd_rfb_defconfig - SD + SPI-NOR (spi2)

Note: spi2 also supports booting from SPI-NAND, but not the default option.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao 2025-01-23 16:55:05 +08:00 committed by Tom Rini
parent 2d6962e061
commit c80a3fb961
13 changed files with 603 additions and 0 deletions

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// SPDX-License-Identifier: GPL-2.0
#include "mt7987a-u-boot.dtsi"
#include "mt7987-netsys-u-boot.dtsi"
/ {
model = "mt7987";
compatible = "mediatek,mt7987", "mediatek,mt7987-emmc-rfb";
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins>;
phy-mode = "2500base-x";
mediatek,switch = "auto";
reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins_default>;
max-frequency = <48000000>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
/delete-node/ spi_nor@0;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "mt7987a.dtsi"
#include "mt7987-emmc.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "MediaTek MT7987 EMMC RFB";
compatible = "mediatek,mt7987a-emmc",
"mediatek,mt7987a", "mediatek,mt7987";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11000000 \
pci=pcie_bus_perf ubi.block=0,firmware \
root=/dev/fit0 rootwait";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2025 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#include "mt7987a-u-boot.dtsi"
#include "mt7987-netsys-u-boot.dtsi"
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins>;
phy-mode = "2500base-x";
mediatek,switch = "auto";
reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
/delete-node/ spi_nand@0;
spi_nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
/delete-node/ spi_nor@0;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "mt7987a.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "MediaTek MT7987A RFB";
compatible = "mediatek,mt7987a", "mediatek,mt7987";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11000000 \
pci=pcie_bus_perf";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0
#include "mt7987a-u-boot.dtsi"
#include "mt7987-netsys-u-boot.dtsi"
/ {
model = "mt7987";
compatible = "mediatek,mt7987", "mediatek,mt7987-sd-rfb";
};
&eth0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins>;
phy-mode = "2500base-x";
mediatek,switch = "auto";
reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
max-frequency = <48000000>;
bus-width = <4>;
cap-sd-highspeed;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_flash_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
must_tx;
enhance_timing;
dma_ext;
ipm_design;
support_quad;
tick_dly = <2>;
sample_sel = <0>;
/delete-node/ spi_nor@0;
spi_nor@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <52000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "mt7987a.dtsi"
#include "mt7987-sd.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "MediaTek MT7987 SD RFB";
compatible = "mediatek,mt7987a-sd",
"mediatek,mt7987a", "mediatek,mt7987";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
earlycon=uart8250,mmio32,0x11000000 \
pci=pcie_bus_perf ubi.block=0,firmware \
root=/dev/fit0 rootwait";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 0 GPIO_ACTIVE_LOW>;
debounce-interval = <10>;
};
};
};

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MT7987
M: Sam Shih <sam.shih@mediatek.com>
S: Maintained
F: board/mediatek/mt7987
F: include/configs/mt7987.h
F: configs/mt7987_rfb_defconfig
F: configs/mt7987_emmc_rfb_defconfig
F: configs/mt7987_sd_rfb_defconfig

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# SPDX-License-Identifier: GPL-2.0
obj-y += mt7987_rfb.o

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2025 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
int board_init(void)
{
return 0;
}

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CONFIG_ARM=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7987a-emmc-rfb"
CONFIG_TARGET_MT7987=y
CONFIG_SYS_BOOTM_LEN=0x6000000
CONFIG_SYS_LOAD_ADDR=0x48000000
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7987a-emmc-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7987> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MTK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_PUYA=y
CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7987=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y

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CONFIG_ARM=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7987a-rfb"
CONFIG_TARGET_MT7987=y
CONFIG_SYS_BOOTM_LEN=0x6000000
CONFIG_SYS_LOAD_ADDR=0x48000000
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7987> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MTK=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_PUYA=y
CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7987=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y

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CONFIG_ARM=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_TEXT_BASE=0x41e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="mt7987a-sd-rfb"
CONFIG_TARGET_MT7987=y
CONFIG_SYS_BOOTM_LEN=0x6000000
CONFIG_SYS_LOAD_ADDR=0x48000000
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7987a-sd-rfb"
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=1049
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_PROMPT="MT7987> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.2"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MTK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_PUYA=y
CONFIG_SPI_FLASH_SILICONKAISER=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MT7987=y
CONFIG_POWER_DOMAIN=y
CONFIG_MTK_POWER_DOMAIN=y
CONFIG_DM_PWM=y
CONFIG_PWM_MTK=y
CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MTK_SPIM=y
CONFIG_HEXDUMP=y

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include/configs/mt7987.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Configuration for MediaTek MT7987 SoC
*
* Copyright (C) 2025 MediaTek Inc.
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#ifndef __MT7987_H
#define __MT7987_H
#define CFG_MAX_MEM_MAPPED 0xC0000000
#endif