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board: dragonboard410c: upstream DT compat
Use the root compatible strings from upstream Linux, add missing '#clock-cells' property to the gcc node. Adjust some of the msm8916/apq8016 drivers to use the correct upstream compatible properties and DT bindings. This prepares us to switch to upstream DT in a future patch. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404 Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly
parent
e9302ba6cc
commit
c744e63089
8 changed files with 246 additions and 96 deletions
arch/arm/dts
board/qualcomm/dragonboard410c
doc/device-tree-bindings/usb
drivers
include/dt-bindings/clock
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@ -12,7 +12,7 @@
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/ {
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model = "Qualcomm Technologies, Inc. Dragonboard 410c";
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compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
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compatible = "qcom,apq8016-sbc", "qcom,apq8016";
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qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
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qcom,board-id = <0x10018 0x0>;
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#address-cells = <0x2>;
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@ -79,6 +79,7 @@
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reg = <0x1800000 0x80000>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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#clock-cells = <0x1>;
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};
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serial@78b0000 {
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@ -91,15 +92,25 @@
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};
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ehci@78d9000 {
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compatible = "qcom,ehci-host";
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compatible = "qcom,ci-hdrc";
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reg = <0x78d9000 0x400>;
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phys = <&ehci_phy>;
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};
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ehci_phy: ehci_phy@78d9000 {
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compatible = "qcom,apq8016-usbphy";
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reg = <0x78d9000 0x400>;
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#phy-cells = <0>;
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ulpi {
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usb_hs_phy: phy {
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compatible = "qcom,usb-hs-phy-msm8916",
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"qcom,usb-hs-phy";
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#phy-cells = <0>;
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clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref", "sleep";
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
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reset-names = "phy", "por";
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qcom,init-seq = /bits/ 8 <0x0 0x44>,
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<0x1 0x6b>,
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<0x2 0x24>,
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<0x3 0x13>;
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};
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};
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};
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sdhci@07824000 {
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@ -9,6 +9,7 @@
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <env.h>
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#include <init.h>
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#include <net.h>
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@ -23,84 +24,32 @@
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#define USB_HUB_RESET_GPIO 2
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#define USB_SW_SELECT_GPIO 3
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int board_usb_init(int index, enum usb_init_type init)
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{
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static struct udevice *pmic_gpio;
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static struct gpio_desc hub_reset, usb_sel;
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int ret = 0, node;
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struct udevice *usb;
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int ret = 0;
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if (!pmic_gpio) {
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ret = uclass_get_device_by_name(UCLASS_GPIO,
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"pm8916_gpios@c000",
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&pmic_gpio);
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if (ret < 0) {
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printf("Failed to find pm8916_gpios@c000 node.\n");
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return ret;
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}
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/* USB device */
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ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
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if (ret) {
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printf("Cannot find USB device\n");
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return ret;
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}
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/* Try to request gpios needed to start usb host on dragonboard */
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if (!dm_gpio_is_valid(&hub_reset)) {
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node = fdt_subnode_offset(gd->fdt_blob,
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dev_of_offset(pmic_gpio),
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"usb_hub_reset_pm");
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if (node < 0) {
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printf("Failed to find usb_hub_reset_pm dt node.\n");
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return node;
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}
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ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
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"gpios", 0, &hub_reset, 0);
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if (ret < 0) {
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printf("Failed to request usb_hub_reset_pm gpio.\n");
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return ret;
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}
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}
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if (!dm_gpio_is_valid(&usb_sel)) {
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node = fdt_subnode_offset(gd->fdt_blob,
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dev_of_offset(pmic_gpio),
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"usb_sw_sel_pm");
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if (node < 0) {
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printf("Failed to find usb_sw_sel_pm dt node.\n");
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return 0;
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}
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ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
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"gpios", 0, &usb_sel, 0);
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if (ret < 0) {
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printf("Failed to request usb_sw_sel_pm gpio.\n");
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return ret;
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}
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}
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if (init == USB_INIT_HOST) {
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/* Start USB Hub */
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dm_gpio_set_dir_flags(&hub_reset,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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mdelay(100);
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/* Switch usb to host connectors */
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dm_gpio_set_dir_flags(&usb_sel,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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mdelay(100);
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} else { /* Device */
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/* Disable hub */
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dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT);
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/* Switch back to device connector */
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dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT);
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/* Select "default" or "device" pinctrl */
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switch (init) {
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case USB_INIT_HOST:
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pinctrl_select_state(usb, "default");
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break;
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case USB_INIT_DEVICE:
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pinctrl_select_state(usb, "device");
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break;
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default:
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debug("Unknown usb_init_type %d\n", init);
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break;
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}
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return 0;
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@ -1,10 +0,0 @@
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Chipidea EHCI controller (part of OTG controller) used on Qualcomm devices.
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Required properties:
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- compatible: must be "qcom,ehci-host"
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- reg: start address and size of the registers
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ehci@78d9000 {
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compatible = "qcom,ehci-host";
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reg = <0x78d9000 0x400>;
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};
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@ -13,6 +13,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include "clock-qcom.h"
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@ -125,13 +126,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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case GCC_SDCC1_APPS_CLK: /* SDC1 */
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return clk_init_sdc(priv, 0, rate);
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break;
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case 1: /* SDC2 */
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case GCC_SDCC2_APPS_CLK: /* SDC2 */
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return clk_init_sdc(priv, 1, rate);
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break;
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case 4: /* UART2 */
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case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
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return clk_init_uart(priv);
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break;
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default:
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@ -74,7 +74,7 @@ static int msm_phy_probe(struct udevice *dev)
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{
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struct msm_phy_priv *priv = dev_get_priv(dev);
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priv->regs = dev_remap_addr(dev);
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priv->regs = dev_remap_addr(dev_get_parent(dev));
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if (!priv->regs)
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return -EINVAL;
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@ -96,7 +96,7 @@ static struct phy_ops msm_phy_ops = {
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};
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static const struct udevice_id msm_phy_ids[] = {
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{ .compatible = "qcom,apq8016-usbphy" },
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{ .compatible = "qcom,usb-hs-phy-msm8916" },
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{ }
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};
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@ -29,7 +29,7 @@ static const char * const msm_pinctrl_pins[] = {
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};
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static const struct pinctrl_function msm_pinctrl_functions[] = {
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{"blsp1_uart", 2},
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{"blsp_uart2", 2},
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};
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static const char *apq8016_get_function_name(struct udevice *dev,
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@ -9,6 +9,7 @@
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#include <common.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <errno.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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@ -119,6 +120,24 @@ static int ehci_usb_of_to_plat(struct udevice *dev)
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return 0;
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}
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static int ehci_usb_of_bind(struct udevice *dev)
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{
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ofnode ulpi_node = ofnode_first_subnode(dev_ofnode(dev));
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ofnode phy_node;
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if (!ofnode_valid(ulpi_node))
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return 0;
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phy_node = ofnode_first_subnode(ulpi_node);
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if (!ofnode_valid(phy_node)) {
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printf("%s: ulpi subnode with no phy\n", __func__);
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return -ENOENT;
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}
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return device_bind_driver_to_node(dev, "msm8916_usbphy", "msm8916_usbphy",
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phy_node, NULL);
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}
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#if defined(CONFIG_CI_UDC)
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/* Little quirk that MSM needs with Chipidea controller
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* Must reinit phy after reset
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@ -132,7 +151,7 @@ void ci_init_after_reset(struct ehci_ctrl *ctrl)
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#endif
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "qcom,ehci-host", },
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{ .compatible = "qcom,ci-hdrc", },
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{ }
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};
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@ -141,6 +160,7 @@ U_BOOT_DRIVER(usb_ehci) = {
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.of_to_plat = ehci_usb_of_to_plat,
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.bind = ehci_usb_of_bind,
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.probe = ehci_usb_probe,
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.remove = ehci_usb_remove,
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.ops = &ehci_usb_ops,
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179
include/dt-bindings/clock/qcom,gcc-msm8916.h
Normal file
179
include/dt-bindings/clock/qcom,gcc-msm8916.h
Normal file
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@ -0,0 +1,179 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2015 Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
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#define GPLL0 0
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#define GPLL0_VOTE 1
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#define BIMC_PLL 2
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#define BIMC_PLL_VOTE 3
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#define GPLL1 4
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#define GPLL1_VOTE 5
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#define GPLL2 6
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#define GPLL2_VOTE 7
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#define PCNOC_BFDCD_CLK_SRC 8
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#define SYSTEM_NOC_BFDCD_CLK_SRC 9
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#define CAMSS_AHB_CLK_SRC 10
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#define APSS_AHB_CLK_SRC 11
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#define CSI0_CLK_SRC 12
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#define CSI1_CLK_SRC 13
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#define GFX3D_CLK_SRC 14
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#define VFE0_CLK_SRC 15
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
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#define BLSP1_UART1_APPS_CLK_SRC 28
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#define BLSP1_UART2_APPS_CLK_SRC 29
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#define CCI_CLK_SRC 30
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#define CAMSS_GP0_CLK_SRC 31
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#define CAMSS_GP1_CLK_SRC 32
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#define JPEG0_CLK_SRC 33
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#define MCLK0_CLK_SRC 34
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#define MCLK1_CLK_SRC 35
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#define CSI0PHYTIMER_CLK_SRC 36
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#define CSI1PHYTIMER_CLK_SRC 37
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#define CPP_CLK_SRC 38
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#define CRYPTO_CLK_SRC 39
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#define GP1_CLK_SRC 40
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#define GP2_CLK_SRC 41
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#define GP3_CLK_SRC 42
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#define BYTE0_CLK_SRC 43
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#define ESC0_CLK_SRC 44
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#define MDP_CLK_SRC 45
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#define PCLK0_CLK_SRC 46
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#define VSYNC_CLK_SRC 47
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#define PDM2_CLK_SRC 48
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#define SDCC1_APPS_CLK_SRC 49
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#define SDCC2_APPS_CLK_SRC 50
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#define APSS_TCU_CLK_SRC 51
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#define USB_HS_SYSTEM_CLK_SRC 52
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#define VCODEC0_CLK_SRC 53
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#define GCC_BLSP1_AHB_CLK 54
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#define GCC_BLSP1_SLEEP_CLK 55
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
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#define GCC_BLSP1_UART1_APPS_CLK 68
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#define GCC_BLSP1_UART2_APPS_CLK 69
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#define GCC_BOOT_ROM_AHB_CLK 70
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#define GCC_CAMSS_CCI_AHB_CLK 71
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#define GCC_CAMSS_CCI_CLK 72
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#define GCC_CAMSS_CSI0_AHB_CLK 73
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#define GCC_CAMSS_CSI0_CLK 74
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#define GCC_CAMSS_CSI0PHY_CLK 75
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#define GCC_CAMSS_CSI0PIX_CLK 76
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#define GCC_CAMSS_CSI0RDI_CLK 77
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#define GCC_CAMSS_CSI1_AHB_CLK 78
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#define GCC_CAMSS_CSI1_CLK 79
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#define GCC_CAMSS_CSI1PHY_CLK 80
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#define GCC_CAMSS_CSI1PIX_CLK 81
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#define GCC_CAMSS_CSI1RDI_CLK 82
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#define GCC_CAMSS_CSI_VFE0_CLK 83
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#define GCC_CAMSS_GP0_CLK 84
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#define GCC_CAMSS_GP1_CLK 85
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#define GCC_CAMSS_ISPIF_AHB_CLK 86
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#define GCC_CAMSS_JPEG0_CLK 87
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#define GCC_CAMSS_JPEG_AHB_CLK 88
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#define GCC_CAMSS_JPEG_AXI_CLK 89
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#define GCC_CAMSS_MCLK0_CLK 90
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#define GCC_CAMSS_MCLK1_CLK 91
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#define GCC_CAMSS_MICRO_AHB_CLK 92
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
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#define GCC_CAMSS_AHB_CLK 95
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#define GCC_CAMSS_TOP_AHB_CLK 96
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#define GCC_CAMSS_CPP_AHB_CLK 97
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#define GCC_CAMSS_CPP_CLK 98
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#define GCC_CAMSS_VFE0_CLK 99
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#define GCC_CAMSS_VFE_AHB_CLK 100
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#define GCC_CAMSS_VFE_AXI_CLK 101
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#define GCC_CRYPTO_AHB_CLK 102
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#define GCC_CRYPTO_AXI_CLK 103
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#define GCC_CRYPTO_CLK 104
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#define GCC_OXILI_GMEM_CLK 105
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#define GCC_GP1_CLK 106
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#define GCC_GP2_CLK 107
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#define GCC_GP3_CLK 108
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#define GCC_MDSS_AHB_CLK 109
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#define GCC_MDSS_AXI_CLK 110
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#define GCC_MDSS_BYTE0_CLK 111
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#define GCC_MDSS_ESC0_CLK 112
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#define GCC_MDSS_MDP_CLK 113
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#define GCC_MDSS_PCLK0_CLK 114
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#define GCC_MDSS_VSYNC_CLK 115
|
||||
#define GCC_MSS_CFG_AHB_CLK 116
|
||||
#define GCC_OXILI_AHB_CLK 117
|
||||
#define GCC_OXILI_GFX3D_CLK 118
|
||||
#define GCC_PDM2_CLK 119
|
||||
#define GCC_PDM_AHB_CLK 120
|
||||
#define GCC_PRNG_AHB_CLK 121
|
||||
#define GCC_SDCC1_AHB_CLK 122
|
||||
#define GCC_SDCC1_APPS_CLK 123
|
||||
#define GCC_SDCC2_AHB_CLK 124
|
||||
#define GCC_SDCC2_APPS_CLK 125
|
||||
#define GCC_GTCU_AHB_CLK 126
|
||||
#define GCC_JPEG_TBU_CLK 127
|
||||
#define GCC_MDP_TBU_CLK 128
|
||||
#define GCC_SMMU_CFG_CLK 129
|
||||
#define GCC_VENUS_TBU_CLK 130
|
||||
#define GCC_VFE_TBU_CLK 131
|
||||
#define GCC_USB2A_PHY_SLEEP_CLK 132
|
||||
#define GCC_USB_HS_AHB_CLK 133
|
||||
#define GCC_USB_HS_SYSTEM_CLK 134
|
||||
#define GCC_VENUS0_AHB_CLK 135
|
||||
#define GCC_VENUS0_AXI_CLK 136
|
||||
#define GCC_VENUS0_VCODEC0_CLK 137
|
||||
#define BIMC_DDR_CLK_SRC 138
|
||||
#define GCC_APSS_TCU_CLK 139
|
||||
#define GCC_GFX_TCU_CLK 140
|
||||
#define BIMC_GPU_CLK_SRC 141
|
||||
#define GCC_BIMC_GFX_CLK 142
|
||||
#define GCC_BIMC_GPU_CLK 143
|
||||
#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
|
||||
#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
|
||||
#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
|
||||
#define ULTAUDIO_XO_CLK_SRC 147
|
||||
#define ULTAUDIO_AHBFABRIC_CLK_SRC 148
|
||||
#define CODEC_DIGCODEC_CLK_SRC 149
|
||||
#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
|
||||
#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
|
||||
#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
|
||||
#define GCC_ULTAUDIO_STC_XO_CLK 153
|
||||
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
|
||||
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
|
||||
#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
|
||||
#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
|
||||
#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
|
||||
#define GCC_CODEC_DIGCODEC_CLK 159
|
||||
#define GCC_MSS_Q6_BIMC_AXI_CLK 160
|
||||
|
||||
/* Indexes for GDSCs */
|
||||
#define BIMC_GDSC 0
|
||||
#define VENUS_GDSC 1
|
||||
#define MDSS_GDSC 2
|
||||
#define JPEG_GDSC 3
|
||||
#define VFE_GDSC 4
|
||||
#define OXILI_GDSC 5
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue