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mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar
Add support for parallel memories and stacked memories configuration in read_bar and write_bar functions. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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1 changed files with 47 additions and 8 deletions
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@ -928,12 +928,32 @@ static int clean_bar(struct spi_nor *nor)
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static int write_bar(struct spi_nor *nor, u32 offset)
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static int write_bar(struct spi_nor *nor, u32 offset)
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{
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{
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u8 cmd, bank_sel;
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u8 cmd, bank_sel, upage_curr;
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int ret;
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int ret;
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struct mtd_info *mtd = &nor->mtd;
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bank_sel = offset / SZ_16M;
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/* Wait until previous write command is finished */
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if (bank_sel == nor->bank_curr)
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if (spi_nor_wait_till_ready(nor))
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goto bar_end;
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return 1;
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if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED) &&
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mtd->size <= SZ_32M)
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return 0;
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if (mtd->size <= SZ_16M)
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return 0;
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offset = offset % (u32)mtd->size;
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bank_sel = offset >> 24;
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upage_curr = nor->spi->flags & SPI_XFER_U_PAGE;
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if (!(nor->flags & SNOR_F_HAS_STACKED) && bank_sel == nor->bank_curr)
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return 0;
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else if (upage_curr == nor->upage_prev && bank_sel == nor->bank_curr)
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return 0;
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nor->upage_prev = upage_curr;
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cmd = nor->bank_write_cmd;
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cmd = nor->bank_write_cmd;
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write_enable(nor);
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write_enable(nor);
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@ -943,15 +963,19 @@ static int write_bar(struct spi_nor *nor, u32 offset)
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return ret;
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return ret;
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}
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}
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bar_end:
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nor->bank_curr = bank_sel;
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nor->bank_curr = bank_sel;
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return nor->bank_curr;
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return write_disable(nor);
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}
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}
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static int read_bar(struct spi_nor *nor, const struct flash_info *info)
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static int read_bar(struct spi_nor *nor, const struct flash_info *info)
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{
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{
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u8 curr_bank = 0;
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u8 curr_bank = 0;
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int ret;
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int ret;
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struct mtd_info *mtd = &nor->mtd;
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if (mtd->size <= SZ_16M)
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return 0;
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switch (JEDEC_MFR(info)) {
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switch (JEDEC_MFR(info)) {
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case SNOR_MFR_SPANSION:
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case SNOR_MFR_SPANSION:
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@ -963,15 +987,30 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info)
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nor->bank_write_cmd = SPINOR_OP_WREAR;
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nor->bank_write_cmd = SPINOR_OP_WREAR;
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}
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}
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if (nor->flags & SNOR_F_HAS_PARALLEL)
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nor->spi->flags |= SPI_XFER_LOWER;
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ret = nor->read_reg(nor, nor->bank_read_cmd,
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ret = nor->read_reg(nor, nor->bank_read_cmd,
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&curr_bank, 1);
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&curr_bank, 1);
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if (ret) {
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if (ret) {
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debug("SF: fail to read bank addr register\n");
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debug("SF: fail to read bank addr register\n");
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return ret;
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return ret;
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}
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}
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nor->bank_curr = curr_bank;
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nor->bank_curr = curr_bank;
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return 0;
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// Make sure both chips use the same BAR
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if (nor->flags & SNOR_F_HAS_PARALLEL) {
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write_enable(nor);
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ret = nor->write_reg(nor, nor->bank_write_cmd, &curr_bank, 1);
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if (ret)
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return ret;
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ret = write_disable(nor);
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if (ret)
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return ret;
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}
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return ret;
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}
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}
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#endif
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#endif
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