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Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-15 12:03:55 -04:00
parent bca4509d57
commit c24e8e2bb3
55 changed files with 54 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
README
View file

@ -2079,12 +2079,6 @@ Low Level (hardware related) configuration options:
one, specify here. Note that the value must resolve
to something your driver can deal with.
- CONFIG_SYS_DDR_RAW_TIMING
Get DDR timing information from other than SPD. Common with
soldered DDR chips onboard without SPD. DDR raw timing
parameters are extracted from datasheet and hard-coded into
header files or board specific files.
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PA_36BIT_NOR_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View file

@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PA_NAND_defconfig
View file

@ -81,6 +81,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PA_NOR_defconfig
View file

@ -48,6 +48,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

1
configs/P1010RDB-PA_SDCARD_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View file

@ -83,6 +83,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_36BIT_NOR_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View file

@ -75,6 +75,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_NAND_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_NOR_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_COMMON_INIT_DDR=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y

1
configs/P1010RDB-PB_SDCARD_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View file

@ -74,6 +74,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View file

@ -80,6 +80,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PC_36BIT_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PC_NAND_defconfig
View file

@ -79,6 +79,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

1
configs/P1020RDB-PC_SDCARD_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PC_defconfig
View file

@ -48,6 +48,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PD_NAND_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8796

1
configs/P1020RDB-PD_SDCARD_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View file

@ -75,6 +75,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P1020RDB-PD_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View file

@ -84,6 +84,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -74,6 +74,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -77,6 +77,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_36BIT_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_NAND_defconfig
View file

@ -83,6 +83,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396

1
configs/P2020RDB-PC_SDCARD_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View file

@ -76,6 +76,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/P2020RDB-PC_defconfig
View file

@ -52,6 +52,7 @@ CONFIG_LBA48=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_SPD_BUS_NUM=1
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7

1
configs/ls1021aqds_nand_defconfig
View file

@ -95,6 +95,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_nor_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_nor_lpuart_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_qspi_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_sdcard_ifc_defconfig
View file

@ -93,6 +93,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021aqds_sdcard_qspi_defconfig
View file

@ -89,6 +89,7 @@ CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_SECURE_BOOT_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_tfa_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_DDR_RAW_TIMING=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

7
drivers/ddr/fsl/Kconfig
View file

@ -175,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER
Use the DDR controller to auto initialize memory. If not enabled,
the DMA controller is responsible for doing this.
config SYS_DDR_RAW_TIMING
bool "Get DDR timing information from something other than SPD"
help
This is common with soldered DDR chips onboard without SPD. DDR raw
timing parameters are extracted from datasheet and hard-coded into
header files or board specific files.
endif
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"

1
include/configs/P1010RDB.h
View file

@ -109,7 +109,6 @@
#define CONFIG_L2_CACHE /* toggle L2 cache */
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef

1
include/configs/T102xRDB.h
View file

@ -129,7 +129,6 @@
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_SDRAM_SIZE 2048
#endif

4
include/configs/ls1021aqds.h
View file

@ -24,10 +24,6 @@
#define SPD_EEPROM_ADDRESS 0x51
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

1
include/configs/ls1043ardb.h
View file

@ -13,7 +13,6 @@
/* Physical Memory Map */
#ifndef CONFIG_SPL
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

4
include/configs/ls2080a_common.h
View file

@ -16,10 +16,6 @@
/* Link Definitions */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
#define CONFIG_VERY_BIG_RAM

1
include/configs/p1_p2_rdb_pc.h
View file

@ -115,7 +115,6 @@
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
#define SPD_EEPROM_ADDRESS 0x52
#if defined(CONFIG_TARGET_P1020RDB_PD)