From 4e73c627cb5e53a058b8dbc2ede32f8a473acdd1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:29 -0500 Subject: [PATCH 01/12] clk: imx6q: Properly handle imx6qp ECSPI clk_sels The ECSPI clock has the ability to select between pll3_60m and osc on the imx6qp, where it's fixed on other variants. Fix this by adding using a helper function to determine SoC variant and register the clock accordingly. Signed-off-by: Adam Ford Reviewed-by: Michael Trimarchi Reviewed-by: Peng Fan --- drivers/clk/imx/clk-imx6q.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index df9f0285e1e..ba75fd1aad6 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; static int imx6q_clk_probe(struct udevice *dev) { @@ -78,6 +79,11 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); + if (of_machine_is_compatible("fsl,imx6qp")) + clk_dm(IMX6QDL_CLK_ECSPI_SEL, + imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, + ARRAY_SIZE(ecspi_sels))); + clk_dm(IMX6QDL_CLK_USDHC1_PODF, imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); @@ -91,8 +97,12 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); - clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + if (of_machine_is_compatible("fsl,imx6qp")) + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + else + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); From c60bdd27401131ef46e6127e293ea489855a3cef Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:30 -0500 Subject: [PATCH 02/12] clk: imx6q: Register UART clocks In order to use the driver model and clock system to enable UART clocks from the serial driver, it's necessary to register the UART clocks. With the helper function to check for imx6qp vs other variants, the UART can register for both scenarios. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- drivers/clk/imx/clk-imx6q.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba75fd1aad6..61ca2982add 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *const uart_sels[] = { "pll3_80m", "osc", }; static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; static int imx6q_clk_probe(struct udevice *dev) @@ -79,10 +80,14 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); - if (of_machine_is_compatible("fsl,imx6qp")) + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_UART_SEL, + imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, + ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels))); + } clk_dm(IMX6QDL_CLK_USDHC1_PODF, imx_clk_divider("usdhc1_podf", "usdhc1_sel", @@ -97,12 +102,17 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); - if (of_machine_is_compatible("fsl,imx6qp")) + if (of_machine_is_compatible("fsl,imx6qp")) { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); - else + } else { + clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, + imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + } clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -112,6 +122,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4)); clk_dm(IMX6QDL_CLK_ECSPI4, imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6)); + clk_dm(IMX6QDL_CLK_UART_IPG, + imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24)); + clk_dm(IMX6QDL_CLK_UART_SERIAL, + imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26)); clk_dm(IMX6QDL_CLK_USDHC1, imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, From 6d33ca36e3b193cd3131b21df9fbba1d828aa31f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:31 -0500 Subject: [PATCH 03/12] clk: imx8mm: register UART clocks In order to let the serial driver enable the clocks, the UART clocks must be registered first. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index bb6958f0ec2..378c07caba3 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -81,6 +81,22 @@ static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m" "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", + "audio_pll2_out", }; + +static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", + "audio_pll2_out", }; + +static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4", + "audio_pll2_out", }; + +static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", + "audio_pll2_out", }; + #if CONFIG_IS_ENABLED(PCIE_DW_IMX) static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", @@ -322,6 +338,24 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); clk_dm(IMX8MM_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); + + clk_dm(IMX8MM_CLK_UART1, + imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MM_CLK_UART2, + imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MM_CLK_UART3, + imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000)); + clk_dm(IMX8MM_CLK_UART4, + imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080)); + clk_dm(IMX8MM_CLK_UART1_ROOT, + imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MM_CLK_UART2_ROOT, + imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MM_CLK_UART3_ROOT, + imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MM_CLK_UART4_ROOT, + imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MM_CLK_WDOG, imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900)); clk_dm(IMX8MM_CLK_USDHC3, From 8999b76f2385cf3b6c01b9be2d7ea84047f4832b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:32 -0500 Subject: [PATCH 04/12] clk: imx8mn: register UART clocks In order to let the serial driver enable the clocks, the UART clocks must be registered first. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- drivers/clk/imx/clk-imx8mn.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index be15ebd0e25..54ae887817a 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -97,6 +97,22 @@ static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m" "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + #ifndef CONFIG_XPL_BUILD static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext1", @@ -311,6 +327,14 @@ static int imx8mn_clk_probe(struct udevice *dev) imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00)); clk_dm(IMX8MN_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MN_CLK_UART1, + imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MN_CLK_UART2, + imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MN_CLK_UART3, + imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000)); + clk_dm(IMX8MN_CLK_UART4, + imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080)); clk_dm(IMX8MN_CLK_WDOG, imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900)); clk_dm(IMX8MN_CLK_USDHC3, @@ -355,6 +379,14 @@ static int imx8mn_clk_probe(struct udevice *dev) imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand)); + clk_dm(IMX8MN_CLK_UART1_ROOT, + imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MN_CLK_UART2_ROOT, + imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MN_CLK_UART3_ROOT, + imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MN_CLK_UART4_ROOT, + imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT, imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); From dda454e933c636b225eef325f5f2b815ed01ac2e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:33 -0500 Subject: [PATCH 05/12] serial: mxc: Support bulk enabling clocks Depending on the platform, there may be multiple clock sources required to enable a UART. Use the bulk functions to get and enable the clocks when the UART probes. This can facilitate the removal of functions to manually enable the clock. This is made dependent on CLK_CCF which is used on imx6q, imx8m[mnqp], several imxrt, imx9. If/when the UART clock registration is done for older boards, this limitation could be updated. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- drivers/serial/serial_mxc.c | 11 +++++++++++ include/dm/platform_data/serial_mxc.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index c5fd740be4d..28f4435d01d 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -3,6 +3,7 @@ * (c) 2007 Sascha Hauer */ +#include #include #include #include @@ -312,7 +313,17 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate) static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_plat *plat = dev_get_plat(dev); +#if CONFIG_IS_ENABLED(CLK_CCF) + int ret; + ret = clk_get_bulk(dev, &plat->clks); + if (ret) + return ret; + + ret = clk_enable_bulk(&plat->clks); + if (ret) + return ret; +#endif _mxc_serial_init(plat->reg, plat->use_dte); return 0; diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h index cc59eeb1dd1..52657aa3deb 100644 --- a/include/dm/platform_data/serial_mxc.h +++ b/include/dm/platform_data/serial_mxc.h @@ -9,6 +9,9 @@ /* Information about a serial port */ struct mxc_serial_plat { struct mxc_uart *reg; /* address of registers in physical memory */ +#if CONFIG_IS_ENABLED(CLK_CCF) + struct clk_bulk clks; +#endif bool use_dte; }; From 0e5c4273537b0da1c18497ecfe0b451ec1a99029 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:34 -0500 Subject: [PATCH 06/12] board: beacon: imx8mm: Let clock system enable UART clock Now that the UART driver can enable the required clocks, remove the hard-coded clock enable. This requires a small re-order of a couple functions. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- board/beacon/imx8mm/spl.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 12013aa5a4d..93ee5b7ee0c 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -100,9 +100,6 @@ void board_init_f(ulong dummy) int ret; arch_cpu_init(); - - init_uart_clk(1); - timer_init(); /* Clear the BSS. */ @@ -114,8 +111,6 @@ void board_init_f(ulong dummy) hang(); } - preloader_console_init(); - ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); @@ -124,6 +119,7 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); enable_tzc380(); power_init_board(); From e066636eed9d5e6261758e03a2e5433c2bee7ce8 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:35 -0500 Subject: [PATCH 07/12] board: beacon: imx8mn: Let clock system enable UART clock Now that the UART driver can enable the required clocks, remove the hard-coded clock enable. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- board/beacon/imx8mn/spl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index f03841e5a01..e91d3fdcf5e 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -111,8 +111,6 @@ int board_early_init_f(void) /* Claiming pwm pins prevents LCD flicker during startup*/ imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); - init_uart_clk(1); - return 0; } From 225b3a778348e28371016d076c36a49fd2565e77 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:36 -0500 Subject: [PATCH 08/12] clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MP If SPL_CLK_IMX8MP is selected alone, it causes a build error. The clock composite is required when using the clock framework, so select it when SPL_CLK_IMX8MP is enabled. This is already being done outside of SPL. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- drivers/clk/imx/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 56d893e0579..d17a54fb9b3 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -60,6 +60,7 @@ config SPL_CLK_IMX8MP depends on ARCH_IMX8M && SPL select SPL_CLK select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF help This enables SPL DM/DTS support for clock driver in i.MX8MP From 7947c8be0e1c930456d7d9a0376485a9ccf7cf09 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:37 -0500 Subject: [PATCH 09/12] configs: imx8mp_beacon: Select SPL_CLK_IMX8MP In preparation to remove manual references for enabling some clocks, enable SPL_CLK_IMX8MP which automatically enables SPL_CCF and SPL_CLK_COMPOSITE_CCF which permit various drivers to activate their respective clocks automatically. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- configs/imx8mp_beacon_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index a69e2ba4c7b..288626c1511 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -87,6 +87,7 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x42800000 From 43f01332714940d3430fbd283d54d848d9934b07 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 18 Mar 2025 18:38:38 -0500 Subject: [PATCH 10/12] board: beacon: imx8mp: Let clock system enable UART clock Now that the UART driver can enable the required clocks, remove the hard-coded clock enable. Signed-off-by: Adam Ford Reviewed-by: Peng Fan --- board/beacon/imx8mp/spl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 30d577f7e0e..6b357d90a3f 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -112,8 +112,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - ret = spl_early_init(); if (ret) { debug("spl_init() failed: %d\n", ret); From ee82a5a0ed0c66005e6884d24f8013c8e62f5a0a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 14 Mar 2025 19:29:16 -0600 Subject: [PATCH 11/12] phycore_imx8mp: Rework some of the RAM related Kconfig symbols As the code is today, we get a warning about "select" statements on "choice" options not doing anything. In this case we can easily fix this by dropping the select line as the following choice statement handles things correctly. We also drop the "default false" line as false / n is the default. Signed-off-by: Tom Rini Reviewed-by: Teresa Remmet --- board/phytec/phycore_imx8mp/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index bdf9e97beaa..caf9cb0c3c3 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -45,7 +45,6 @@ config PHYCORE_IMX8MP_RAM_SIZE_4GB config PHYCORE_IMX8MP_RAM_SIZE_8GB bool "8GB RAM" - select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS help Set RAM size fix to 8GB for phyCORE-i.MX8MP. Only 2GHz RAMs are supported. @@ -54,7 +53,6 @@ endchoice config PHYCORE_IMX8MP_RAM_FREQ_FIX bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting" - default false help RAM frequency is automatic being detected with the help of the EEPROM introspection data. Set RAM frequency to a fix value From cc9dcba9cce185d8bca2dc5c4b55b21f4505cbe8 Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Wed, 19 Mar 2025 15:25:20 +0800 Subject: [PATCH 12/12] configs: Remove duplicated bootcmd 'mmc dev ${mmcdev}' The 'mmc dev ${mmcdev}' is defined twice, so remove the duplicated one Signed-off-by: Aristo Chen --- configs/mx6sxsabreauto_defconfig | 2 +- configs/mx6ul_14x14_evk_defconfig | 2 +- configs/mx6ul_9x9_evk_defconfig | 2 +- configs/mx6ull_14x14_evk_defconfig | 2 +- configs/mx6ull_14x14_evk_plugin_defconfig | 2 +- configs/mx6ulz_14x14_evk_defconfig | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 870b7a1be10..25b0b11342d 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index f841b21c016..737a079eaa7 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 11a18d16f52..964d00a4085 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 316f74c278b..369bc0f2e0a 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 8be5963a433..97d4f9fc65f 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -15,7 +15,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 2c13dd4dbc3..1a49bc2cf01 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y