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sunxi: refactor serial base addresses to avoid asm/arch/cpu.h

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At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.

Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.

This disentangles the architecture specific header files from the
generic code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2022-07-03 00:14:24 +01:00
parent 5b7c58fbba
commit beeace9ba1
12 changed files with 40 additions and 32 deletions
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1
arch/arm/cpu/armv7/sunxi/sram.c
View file

@ -12,6 +12,7 @@
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
void sunxi_sram_init(void)
{

1
arch/arm/cpu/armv8/fel_utils.S
View file

@ -10,6 +10,7 @@
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/arch/cpu.h>
/*
* We don't overwrite save_boot_params() here, to save the FEL state upon

2
arch/arm/include/asm/arch-sunxi/boot0.h
View file

@ -3,6 +3,8 @@
* Configuration settings for the Allwinner A64 (sun50i) CPU
*/
#include <asm/arch/cpu.h>
#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
/* reserve space for BOOT0 header information */
b reset

1
arch/arm/include/asm/arch-sunxi/clock.h
View file

@ -9,6 +9,7 @@
#define _SUNXI_CLOCK_H
#include <linux/types.h>
#include <asm/arch/cpu.h>
#define CLK_GATE_OPEN 0x1
#define CLK_GATE_CLOSE 0x0

15
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
View file

@ -128,20 +128,6 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
#ifdef CONFIG_MACH_SUNIV
#define SUNXI_UART0_BASE 0x01c25000
#define SUNXI_UART1_BASE 0x01c25400
#define SUNXI_UART2_BASE 0x01c25800
#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
#define SUNXI_UART6_BASE 0x01c29800
#define SUNXI_UART7_BASE 0x01c29c00
#define SUNXI_PS2_0_BASE 0x01c2a000
#define SUNXI_PS2_1_BASE 0x01c2a400
@ -208,7 +194,6 @@ defined(CONFIG_MACH_SUN50I)
#endif
#define SUNXI_R_TWI_BASE 0x01f02400
#define SUNXI_R_UART_BASE 0x01f02800
#define SUN6I_P2WI_BASE 0x01f03400
#define SUNXI_RSB_BASE 0x01f03400

5
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
View file

@ -42,10 +42,6 @@
#define SUNXI_DRAM_PHY0_BASE 0x04800000
#endif
#define SUNXI_UART0_BASE 0x05000000
#define SUNXI_UART1_BASE 0x05000400
#define SUNXI_UART2_BASE 0x05000800
#define SUNXI_UART3_BASE 0x05000C00
#define SUNXI_TWI0_BASE 0x05002000
#define SUNXI_TWI1_BASE 0x05002400
#define SUNXI_TWI2_BASE 0x05002800
@ -67,7 +63,6 @@
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_PRCM_BASE 0x07010000
#define SUNXI_R_WDOG_BASE 0x07020400
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_TWI_BASE 0x07081400
#ifndef __ASSEMBLY__

7
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
View file

@ -86,12 +86,6 @@
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
/* APB1 Module */
#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
@ -100,7 +94,6 @@
/* RCPUS Module */
#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */

4
arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h
View file

@ -10,10 +10,6 @@
#define SUNXI_CCM_BASE 0x02001000
#define SUNXI_TIMER_BASE 0x02050000
#define SUNXI_UART0_BASE 0x02500000
#define SUNXI_UART1_BASE 0x02500400
#define SUNXI_UART2_BASE 0x02500800
#define SUNXI_UART3_BASE 0x02500C00
#define SUNXI_TWI0_BASE 0x02502000
#define SUNXI_TWI1_BASE 0x02502400
#define SUNXI_TWI2_BASE 0x02502800

32
arch/arm/include/asm/arch-sunxi/serial.h Normal file
View file

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* hardcoded UART base addresses for early SPL use
*
* Copyright (c) 2022 Arm Ltd.
*/
#ifndef SUNXI_SERIAL_MEMMAP_H
#define SUNXI_SERIAL_MEMMAP_H
#if defined(CONFIG_MACH_SUN9I)
#define SUNXI_UART0_BASE 0x07000000
#define SUNXI_R_UART_BASE 0x08002800
#elif defined(CONFIG_SUN50I_GEN_H6)
#define SUNXI_UART0_BASE 0x05000000
#define SUNXI_R_UART_BASE 0x07080000
#elif defined(CONFIG_MACH_SUNIV)
#define SUNXI_UART0_BASE 0x01c25000
#define SUNXI_R_UART_BASE 0
#elif defined(CONFIG_SUNXI_GEN_NCAT2)
#define SUNXI_UART0_BASE 0x02500000
#define SUNXI_R_UART_BASE 0 // 0x07080000 (?>
#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_R_UART_BASE 0x01f02800
#endif
#define SUNXI_UART1_BASE (SUNXI_UART0_BASE + 0x400)
#define SUNXI_UART2_BASE (SUNXI_UART0_BASE + 0x800)
#define SUNXI_UART3_BASE (SUNXI_UART0_BASE + 0xc00)
#endif /* SUNXI_SERIAL_MEMMAP_H */

1
arch/arm/mach-sunxi/gtbus_sun9i.c
View file

@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gtbus_sun9i.h>
#include <asm/arch/sys_proto.h>

1
arch/arm/mach-sunxi/timer.c
View file

@ -10,6 +10,7 @@
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/timer.h>
#include <linux/delay.h>

2
include/configs/sunxi-common.h
View file

@ -12,7 +12,6 @@
#ifndef _SUNXI_COMMON_CONFIG_H
#define _SUNXI_COMMON_CONFIG_H
#include <asm/arch/cpu.h>
#include <linux/stringify.h>
/* Serial & console */
@ -24,6 +23,7 @@
#define CFG_SYS_NS16550_CLK 24000000
#endif
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#include <asm/arch/serial.h>
# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE
# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE
# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE