From 9bcf9e49a24e1cd96565b8ccd40b23ab956c3376 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:12 +0900 Subject: [PATCH 01/11] riscv: bootstage: correct bootstage_report guard Below warning can be occurred when CONFIG_BOOTSTAGE and !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED for SPL build. arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of function 'bootstage_report' 46 | bootstage_report(); | ^~~~~~~~~~~~~~~~ | bootstage_error Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 276677a5e2f..cc30efc9049 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake) #ifdef CONFIG_BOOTSTAGE_FDT bootstage_fdt_add_report(); #endif -#ifdef CONFIG_BOOTSTAGE_REPORT +#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT) bootstage_report(); #endif From 74fbd74ed2069985c9d7dd15ffe94f8a95f1022a Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:13 +0900 Subject: [PATCH 02/11] riscv: timer: add timer_get_boot_us for BOOTSTAGE timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/riscv_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 28a6a6870b8..169c03dcb5c 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -51,6 +52,27 @@ u64 notrace timer_early_get_count(void) } #endif +#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + int ret; + u64 ticks = 0; + u32 rate; + + ret = dm_timer_init(); + if (!ret) { + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); + } else { + rate = RISCV_SMODE_TIMER_FREQ; + ticks = riscv_timer_get_count(NULL); + } + + /* Below is converted from time(us) = (tick / rate) * 10000000 */ + return lldiv(ticks * 1000, (rate / 1000)); +} +#endif + static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); From 6d78473b3d390c650aa7f418bdd5044ea42ee951 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 6 Sep 2023 14:18:14 +0900 Subject: [PATCH 03/11] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE timer_get_boot_us function is required to record the boot stages as us-based timestamp. To get a micro-second time from a timer tick, this converts the formula like below to avoid zero result of (tick / rate) part. From: time(us) = (tick / rate) * 1000000 To : time(us) = (tick * 1000) / (rate / 1000) Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/riscv_aclint_timer.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c index e29d527c8d7..73fb8791285 100644 --- a/drivers/timer/riscv_aclint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -44,6 +45,28 @@ u64 notrace timer_early_get_count(void) } #endif +#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + int ret; + u64 ticks = 0; + u32 rate; + + ret = dm_timer_init(); + if (!ret) { + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); + } else { + rate = RISCV_MMODE_TIMER_FREQ; + ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE, + RISCV_MMODE_TIMEROFF)); + } + + /* Below is converted from time(us) = (tick / rate) * 10000000 */ + return lldiv(ticks * 1000, (rate / 1000)); +} +#endif + static const struct timer_ops riscv_aclint_timer_ops = { .get_count = riscv_aclint_timer_get_count, }; From c202426d6ac6bffccf19e958dc176f7d29d0528e Mon Sep 17 00:00:00 2001 From: Kuan Lim Lee Date: Tue, 19 Sep 2023 15:30:36 +0800 Subject: [PATCH 04/11] timer: starfive: Add Starfive timer support Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee Reviewed-by: Wei Liang Lim Reviewed-by: Simon Glass --- drivers/timer/Kconfig | 7 +++ drivers/timer/Makefile | 1 + drivers/timer/starfive-timer.c | 94 ++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 drivers/timer/starfive-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 915b2af160c..a98be9dfae4 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -326,4 +326,11 @@ config XILINX_TIMER Select this to enable support for the timer found on any Xilinx boards (axi timer). +config STARFIVE_TIMER + bool "Starfive timer support" + depends on TIMER + help + Select this to enable support for the timer found on + Starfive SoC. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ca74805fd9..1ef814970b9 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o obj-$(CONFIG_XILINX_TIMER) += xilinx-timer.o +obj-$(CONFIG_STARFIVE_TIMER) += starfive-timer.o diff --git a/drivers/timer/starfive-timer.c b/drivers/timer/starfive-timer.c new file mode 100644 index 00000000000..816402fdbf2 --- /dev/null +++ b/drivers/timer/starfive-timer.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 StarFive, Inc. All rights reserved. + * Author: Lee Kuan Lim + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define STF_TIMER_INT_STATUS 0x00 +#define STF_TIMER_CTL 0x04 +#define STF_TIMER_LOAD 0x08 +#define STF_TIMER_ENABLE 0x10 +#define STF_TIMER_RELOAD 0x14 +#define STF_TIMER_VALUE 0x18 +#define STF_TIMER_INT_CLR 0x20 +#define STF_TIMER_INT_MASK 0x24 + +struct starfive_timer_priv { + void __iomem *base; + u32 timer_size; +}; + +static u64 notrace starfive_get_count(struct udevice *dev) +{ + struct starfive_timer_priv *priv = dev_get_priv(dev); + + /* Read decrement timer value and convert to increment value */ + return priv->timer_size - readl(priv->base + STF_TIMER_VALUE); +} + +static const struct timer_ops starfive_ops = { + .get_count = starfive_get_count, +}; + +static int starfive_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct starfive_timer_priv *priv = dev_get_priv(dev); + int timer_channel; + struct clk clk; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + timer_channel = dev_read_u32_default(dev, "channel", 0); + priv->base = priv->base + (0x40 * timer_channel); + + /* Get clock rate from channel selectecd*/ + ret = clk_get_by_index(dev, timer_channel, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + uc_priv->clock_rate = clk_get_rate(&clk); + + /* Initiate timer, channel 0 */ + /* Unmask Interrupt Mask */ + writel(0, priv->base + STF_TIMER_INT_MASK); + /* Single run mode Setting */ + if (dev_read_bool(dev, "single-run")) + writel(1, priv->base + STF_TIMER_CTL); + /* Set Reload value */ + priv->timer_size = dev_read_u32_default(dev, "timer-size", 0xffffffff); + writel(priv->timer_size, priv->base + STF_TIMER_LOAD); + /* Enable to start timer */ + writel(1, priv->base + STF_TIMER_ENABLE); + + return 0; +} + +static const struct udevice_id starfive_ids[] = { + { .compatible = "starfive,jh8100-timers" }, + { } +}; + +U_BOOT_DRIVER(jh8100_starfive_timer) = { + .name = "jh8100_starfive_timer", + .id = UCLASS_TIMER, + .of_match = starfive_ids, + .probe = starfive_probe, + .ops = &starfive_ops, + .priv_auto = sizeof(struct starfive_timer_priv), +}; From f2e4b9d3c2f858f5ce7e317b2974d74353abb2a2 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 21 Sep 2023 10:42:18 +0200 Subject: [PATCH 05/11] cmd/exception: support RISC-V compressed instruction Eliminating the C extension on application processors is under discussion. Support emitting a compressed instruction. This will lead to an illegal instruction exception if the C extension is not implemented. For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n and run with qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false => exception compressed Unhandled exception: Illegal instruction EPC: 0000000087731708 RA: 000000008773fe44 TVAL: 0000000000004501 EPC: 000000008001b708 RA: 0000000080029e44 reloc adjusted Code: 0b93 0000 0493 0000 0993 0000 f06f ccdf (4501) Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- cmd/riscv/exception.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 7a08061d120..db8d8af0483 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -8,6 +8,15 @@ #include #include +static int do_compressed(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* c.li a0, 0; c.li a0, 0 */ + asm volatile (".long 0x45014501\n"); + printf("The system supports compressed instructions.\n"); + return CMD_RET_SUCCESS; +} + static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -35,6 +44,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_sub[] = { + U_BOOT_CMD_MKENT(compressed, CONFIG_SYS_MAXARGS, 1, do_compressed, + "", ""), U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak, "", ""), U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, @@ -46,9 +57,10 @@ static struct cmd_tbl cmd_sub[] = { static char exception_help_text[] = "\n" " The following exceptions are available:\n" - " ebreak - breakpoint\n" - " undefined - illegal instruction\n" - " unaligned - load address misaligned\n" + " compressed - compressed instruction\n" + " ebreak - breakpoint\n" + " undefined - illegal instruction\n" + " unaligned - load address misaligned\n" ; #include From ef5ccaae64b670bc3183e20378d1fa31c86c9f44 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 21 Sep 2023 12:39:29 +0200 Subject: [PATCH 06/11] cmd/exception: test RISC-V 16 bit aligned instruction A 16 bit aligned instruction should generated an exception if the C extension is not available. Provide an 'extension ialign16' command for testing exception handling. For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n and run with qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false => exception ialign16 Unhandled exception: Instruction address misaligned EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060) Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- cmd/riscv/exception.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index db8d8af0483..f38f454a0b1 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -24,6 +24,19 @@ static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } +static int do_ialign16(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + asm volatile ( + /* jump skipping 2 bytes */ + ".long 0x0060006f\n" + ".long 0x006f0000\n" + ".long 0x00000060\n" + ); + printf("The system supports 16 bit aligned instructions.\n"); + return CMD_RET_SUCCESS; +} + static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -48,6 +61,8 @@ static struct cmd_tbl cmd_sub[] = { "", ""), U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak, "", ""), + U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16, + "", ""), U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, "", ""), U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, @@ -59,6 +74,7 @@ static char exception_help_text[] = " The following exceptions are available:\n" " compressed - compressed instruction\n" " ebreak - breakpoint\n" + " ialign16 - 16 bit aligned instruction\n" " undefined - illegal instruction\n" " unaligned - load address misaligned\n" ; From e637e455ca766d6b5bea5f4c5b9290ab07c87507 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 23 Sep 2023 01:35:26 +0200 Subject: [PATCH 07/11] riscv: enable CONFIG_DEBUG_UART by default Most boards don't enable the pre-console buffer. So we will not see any early messages. OpenSBI 1.3 provides us with the debug console extension that can fill this gap. For S-Mode U-Boot enable CONFIG_DEBUG_UART by default. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1c62c2345b0..06fae7ebe83 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -141,6 +141,7 @@ config RISCV_MMODE config RISCV_SMODE bool "Supervisor" + imply DEBUG_UART help Choose this option to build U-Boot for RISC-V S-Mode. From b68bf22fbb5cbce6f48d979a31a8bfb7230e9512 Mon Sep 17 00:00:00 2001 From: Randolph Date: Mon, 25 Sep 2023 17:24:51 +0800 Subject: [PATCH 08/11] configs: andes: add vender prefix for target name Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph Reviewed-by: Tom Rini --- arch/riscv/Kconfig | 4 ++-- arch/riscv/dts/Makefile | 2 +- board/AndesTech/ae350/Kconfig | 2 +- configs/ae350_rv32_defconfig | 3 ++- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- 11 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 06fae7ebe83..183885ebe7d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AE350 - bool "Support ae350" +config TARGET_ANDES_AE350 + bool "Support Andes ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f1525cb6680..be6c8a42272 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ae350/Kconfig b/board/AndesTech/ae350/Kconfig index 75815bf99aa..a85e7d63517 100644 --- a/board/AndesTech/ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,4 +1,4 @@ -if TARGET_AE350 +if TARGET_ANDES_AE350 config SYS_CPU default "andesv5" diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index ce312a65341..8269b8d6556 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -8,7 +8,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y +CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 7f7ce0373bc..030ef57f071 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 7b0c6575949..e09ab2409a3 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -11,7 +11,7 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 641c10022f8..b90200a97e8 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 02d8c07c81b..a4b9ad6162d 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 4655050f707..5c3e6229635 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -9,7 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index ad721d1870a..3cb3444e92c 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -10,7 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 042d876702e..cc5e751c9b6 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AE350=y +CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x88000000 From 5f2529763772e26ed6c7f7ecbefe9482ad75fb99 Mon Sep 17 00:00:00 2001 From: Randolph Date: Mon, 25 Sep 2023 17:24:52 +0800 Subject: [PATCH 09/11] configs: andes: rearrange SPL mode memory layout Unify the memory layout for u-boot SPL mode Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS" Signed-off-by: Randolph Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_spl_defconfig | 8 +++++--- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 9 ++++++--- configs/ae350_rv64_spl_xip_defconfig | 6 ++++-- 4 files changed, 18 insertions(+), 10 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 030ef57f071..619be521167 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -15,17 +15,19 @@ CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e09ab2409a3..676db37c07d 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -8,7 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -23,10 +23,11 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 5c3e6229635..f67fe807e4d 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -6,7 +6,8 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -15,17 +16,19 @@ CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 +CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 3cb3444e92c..6f8f9f57e5a 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -7,7 +7,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y @@ -23,10 +24,11 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 -CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_START_ADDR=0x400000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y From 8a0d5f2f51b72b3cabacfe90ff196db3e1c4dc4d Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Fri, 29 Sep 2023 12:03:07 +0800 Subject: [PATCH 10/11] riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Samuel Holland --- arch/riscv/cpu/andesv5/Kconfig | 3 ++- drivers/timer/Kconfig | 9 ++++++++- drivers/timer/Makefile | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 82bb5a2a532..f311291aedb 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -4,8 +4,9 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLMT_TIMER + imply SPL_ANDES_PLMT_TIMER imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) imply V5L2_CACHE imply SPL_CPU imply SPL_OPENSBI diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index a98be9dfae4..60519c3b536 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -59,7 +59,14 @@ config ALTERA_TIMER config ANDES_PLMT_TIMER bool - depends on RISCV_MMODE || SPL_RISCV_MMODE + depends on RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + +config SPL_ANDES_PLMT_TIMER + bool + depends on SPL_RISCV_MMODE help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 1ef814970b9..b93145e8d43 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -4,7 +4,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o -obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o +obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o From 7cfdacbe8020292845bd5eba63b576b8586c433c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 1 Oct 2023 07:40:47 +0200 Subject: [PATCH 11/11] configs: sifive: enable poweroff command on Unmatched Powering off the SiFive HiFive Unmatched board is supported both via the SBI and GPIO sysreset drivers. See device-tree entry compatible = "gpio-poweroff". Enable the poweroff command. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- configs/sifive_unmatched_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 867611b6b4e..71c0fb39320 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y CONFIG_ENV_SPI_BUS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y