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clk: clk-imx8qxp: Add LPUART IPG entries

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Since commit cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.

The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.

Fix the boot regression by adding the LPUART IPG entries.

Fixes: cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Fabio Estevam 2024-03-08 17:13:15 -03:00 • committed by Tom Rini
parent 5397daaed8
commit bcbd1364cb
1 changed files with 12 additions and 1 deletions
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13
drivers/clk/imx/clk-imx8qxp.c
View file

@ -88,20 +88,23 @@ ulong imx8_clk_get_rate(struct clk *clk)
resource = SC_R_SDHC_1; resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART0_IPG_CLK:
case IMX8QXP_UART0_CLK: case IMX8QXP_UART0_CLK:
case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0; resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART1_CLK: case IMX8QXP_UART1_CLK:
case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1; resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART2_CLK: case IMX8QXP_UART2_CLK:
case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2; resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART3_CLK: case IMX8QXP_UART3_CLK:
case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3; resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
@ -170,18 +173,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART0_CLK: case IMX8QXP_UART0_CLK:
case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0; resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART1_CLK: case IMX8QXP_UART1_CLK:
case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1; resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART2_CLK: case IMX8QXP_UART2_CLK:
case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2; resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART3_CLK: case IMX8QXP_UART3_CLK:
case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3; resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
@ -263,18 +270,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART0_CLK: case IMX8QXP_UART0_CLK:
case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0; resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART1_CLK: case IMX8QXP_UART1_CLK:
case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1; resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART2_CLK: case IMX8QXP_UART2_CLK:
case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2; resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;
case IMX8QXP_UART3_CLK: case IMX8QXP_UART3_CLK:
case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3; resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER; pm_clk = SC_PM_CLK_PER;
break; break;