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riscv: timer: Add support for an early timer

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Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Pragnesh Patel 2021-01-17 18:11:25 +05:30 • committed by Andes
parent a80f85138c
commit bc8d12bfd8
6 changed files with 75 additions and 3 deletions
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21
drivers/timer/sifive_clint_timer.c
View file

@ -15,11 +15,30 @@
/* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
static u64 sifive_clint_get_count(struct udevice *dev)
static u64 notrace sifive_clint_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
/**
* timer_early_get_rate() - Get the timer rate before driver model
*/
unsigned long notrace timer_early_get_rate(void)
{
return RISCV_MMODE_TIMER_FREQ;
}
/**
* timer_early_get_count() - Get the timer count before driver model
*
*/
u64 notrace timer_early_get_count(void)
{
return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
}
#endif
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};