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arm64: Catch non-emulated semihosting calls

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If a debugger is not attached to U-Boot, semihosting calls will raise a
synchronous abort exception. Try to catch this and disable semihosting
so we can e.g. use another uart if one is available. In the immediate
case, we return an error, since it is not always possible to check for
semihosting beforehand (debug uart, user-initiated load command, etc.)

We handle all possible semihosting instructions, which is probably
overkill. However, we do need to keep track of what instruction set
we're using so that we don't suppress an actual error.

A future enhancement could try to determine semihosting capability by
inspecting the processor state.  There's an example of this at [1] for
RISC-V. The equivalent for ARM would inspect the monitor modei
enable/select bits of the DSCR. However, as the article notes, an
exception handler is still helpful in order to catch disconnected
debuggers.

[1] https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html#avoiding-hangs-when-a-debugger-is-not-connected

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
This commit is contained in:
Sean Anderson 2022-03-22 16:59:31 -04:00 • committed by Tom Rini
parent 385d69d76b
commit bbe310cdaf
2 changed files with 58 additions and 0 deletions
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11
include/semihosting.h
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@ -6,6 +6,17 @@
#ifndef _SEMIHOSTING_H
#define _SEMIHOSTING_H
/*
* These are the encoded instructions used to indicate a semihosting trap. They
* are named like SMH_ISA_INSN, where ISA is the instruction set (e.g.
* AArch64), and INSN is the mneumonic for the instruction.
*/
#define SMH_A64_HLT 0xD45E0000
#define SMH_A32_SVC 0xEF123456
#define SMH_A32_HLT 0xE10F0070
#define SMH_T32_SVC 0xDFAB
#define SMH_T32_HLT 0xBABC
#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
/**
* semihosting_enabled() - Determine whether semihosting is supported