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stm32mp1: psci: add synchronization with ROM code

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Use SGI0 interruption  and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
  RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
  + TAMP_BACKUP_BRANCH_ADDRESS
  + TAMP_BACKUP_MAGIC_NUMBER
  when magic is not egual to
  BOOT_API_A7_CORE0_MAGIC_NUMBER

This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2019-04-18 17:32:40 +02:00 • committed by Patrice Chotard
parent ee7d772370
commit bb7288ef1c
1 changed files with 18 additions and 4 deletions
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22
arch/arm/mach-stm32mp/psci.c
View file

@ -47,14 +47,14 @@ static u32 __secure stm32mp_get_gicd_base_address(void)
return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
} }
static void __secure stm32mp_smp_kick_all_cpus(void) static void __secure stm32mp_raise_sgi0(int cpu)
{ {
u32 gic_dist_addr; u32 gic_dist_addr;
gic_dist_addr = stm32mp_get_gicd_base_address(); gic_dist_addr = stm32mp_get_gicd_base_address();
/* kick all CPUs (except this one) by writing to GICD_SGIR */ /* ask cpu with SGI0 */
writel(1U << 24, gic_dist_addr + GICD_SGIR); writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
} }
void __secure psci_arch_cpu_entry(void) void __secure psci_arch_cpu_entry(void)
@ -62,6 +62,9 @@ void __secure psci_arch_cpu_entry(void)
u32 cpu = psci_get_cpu_id(); u32 cpu = psci_get_cpu_id();
psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
/* reset magic in TAMP register */
writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
} }
int __secure psci_features(u32 function_id, u32 psci_fid) int __secure psci_features(u32 function_id, u32 psci_fid)
@ -127,6 +130,16 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
return ARM_PSCI_RET_ALREADY_ON; return ARM_PSCI_RET_ALREADY_ON;
/* reset magic in TAMP register */
if (readl(TAMP_BACKUP_MAGIC_NUMBER))
writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
/*
* ROM code need a first SGI0 after core reset
* core is ready when magic is set to 0 in ROM code
*/
while (readl(TAMP_BACKUP_MAGIC_NUMBER))
stm32mp_raise_sgi0(cpu);
/* store target PC and context id*/ /* store target PC and context id*/
psci_save(cpu, pc, context_id); psci_save(cpu, pc, context_id);
@ -142,7 +155,8 @@ int __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
TAMP_BACKUP_MAGIC_NUMBER); TAMP_BACKUP_MAGIC_NUMBER);
stm32mp_smp_kick_all_cpus(); /* Generate an IT to start the core */
stm32mp_raise_sgi0(cpu);
return ARM_PSCI_RET_SUCCESS; return ARM_PSCI_RET_SUCCESS;
} }