mirror of
https://github.com/u-boot/u-boot.git
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Merge patch series "Add QOS support for J722S and AM62P"
Jayesh Choudhary <j-choudhary@ti.com> says: Add QOS support for DSS in TI K3 SoC to route the DSS traffic through RT queue by setting orderID as 15: - J722S - AM62P Link: https://lore.kernel.org/r/20241126070614.47136-1-j-choudhary@ti.com
This commit is contained in:
Tom Rini
commit
b83ac2a541
10 changed files with 216 additions and 0 deletions
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@ -159,6 +159,8 @@ void board_init_f(ulong dummy)
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}
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spl_enable_cache();
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setup_qos();
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debug("am62px_init: %s done\n", __func__);
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}
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@ -165,6 +165,7 @@ void board_init_f(ulong dummy)
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{
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k3_spl_init();
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k3_mem_init();
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setup_qos();
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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@ -4,3 +4,4 @@
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obj-y += clk-data.o
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obj-y += dev-data.o
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obj-y += am62p_qos_uboot.o
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42
arch/arm/mach-k3/r5/am62px/am62p_qos.h
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42
arch/arm/mach-k3/r5/am62px/am62p_qos.h
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Keystone3 Quality of service endpoint definitions
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* Auto generated by K3 Resource Partitioning Tool
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
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#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
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#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
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#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
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#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
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#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
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#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
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#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
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#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
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#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
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#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
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#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
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#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
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#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
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#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
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#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
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#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
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#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
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#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
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#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
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#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
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#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
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#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
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#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
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#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45D29800
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#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45D2A000
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#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D30000
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#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
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#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D34000
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#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D34400
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#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
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#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
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#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D35000
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#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D35400
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58
arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
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arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* am62p Quality of Service (QoS) Configuration Data
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <asm/arch/k3-qos.h>
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#include "am62p_qos.h"
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struct k3_qos_data qos_data[] = {
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/* modules_qosConfig0 - 1 endpoints, 4 channels */
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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/* modules_qosConfig1 - 1 endpoints, 4 channels */
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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/* Following registers set 1:1 mapping for orderID MAP1/MAP2
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* remap registers. orderID x is remapped to orderID x again
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* This is to ensure orderID from MAP register is unchanged
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*/
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/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
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/* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
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};
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u32 qos_count = ARRAY_SIZE(qos_data);
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@ -4,3 +4,4 @@
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obj-y += clk-data.o
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obj-y += dev-data.o
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obj-y += j722s_qos_uboot.o
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51
arch/arm/mach-k3/r5/j722s/j722s_qos.h
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51
arch/arm/mach-k3/r5/j722s/j722s_qos.h
Normal file
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@ -0,0 +1,51 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Keystone3 Quality of service endpoint definitions
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* Auto generated by K3 Resource Partitioning Tool
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
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#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
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#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
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#define PULSAR_UL_MAIN_0_CPU0_RMST 0x45D15000
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#define PULSAR_UL_MAIN_0_CPU0_WMST 0x45D15400
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#define PULSAR_UL_MAIN_0_CPU0_PMST 0x45D15800
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#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
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#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
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#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
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#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
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#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
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#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
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#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
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#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
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#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
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#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
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#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
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#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
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#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
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#define USB3P0SS64_16FFC_MAIN_0_MSTR0 0x45D24800
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#define USB3P0SS64_16FFC_MAIN_0_MSTW0 0x45D24C00
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#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
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#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
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#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
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#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
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#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
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#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
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#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
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#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
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#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
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#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD 0x45D29000
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#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR 0x45D29400
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#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45D29800
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#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45D2A000
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#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC 0x45D2C000
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#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D30000
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#define K3_DSS_UL_MAIN_1_VBUSM_DMA 0x45D30400
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#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D34000
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#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D34400
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#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D34800
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#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D34C00
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#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D35000
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#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D35400
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58
arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
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58
arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
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@ -0,0 +1,58 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* j722s Quality of Service (QoS) Configuration Data
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <asm/arch/k3-qos.h>
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#include "j722s_qos.h"
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struct k3_qos_data qos_data[] = {
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/* modules_qosConfig0 - 1 endpoints, 4 channels */
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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/* modules_qosConfig1 - 1 endpoints, 4 channels */
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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{
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.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
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.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
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},
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/* Following registers set 1:1 mapping for orderID MAP1/MAP2
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* remap registers. orderID x is remapped to orderID x again
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* This is to ensure orderID from MAP register is unchanged
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*/
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/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
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/* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
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};
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u32 qos_count = ARRAY_SIZE(qos_data);
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@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_OMAP24XX=y
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CONFIG_DM_MAILBOX=y
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CONFIG_K3_QOS=y
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CONFIG_K3_SEC_PROXY=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_MMC_SDHCI=y
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@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_OMAP24XX=y
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CONFIG_DM_MAILBOX=y
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CONFIG_K3_QOS=y
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CONFIG_K3_SEC_PROXY=y
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CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_MMC_SDHCI=y
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