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ARM: dts: remove leftover Amlogic GX/G12 bindings headers
Remove the leftover Amlogic GX/G12 bindings headers that maked the v6.10 upstream DT fail to build. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
Neil Armstrong
Tom Rini
parent
dce89b3bfc
commit
b79e7edff3
8 changed files with 0 additions and 549 deletions
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (c) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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*/
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#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
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#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
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#define CLKID_AO_REMOTE 0
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#define CLKID_AO_I2C_MASTER 1
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#define CLKID_AO_I2C_SLAVE 2
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#define CLKID_AO_UART1 3
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#define CLKID_AO_UART2 4
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#define CLKID_AO_IR_BLASTER 5
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#define CLKID_AO_SAR_ADC 6
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#define CLKID_AO_CLK81 7
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#define CLKID_AO_SAR_ADC_SEL 8
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#define CLKID_AO_SAR_ADC_DIV 9
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#define CLKID_AO_SAR_ADC_CLK 10
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#define CLKID_AO_CTS_OSCIN 11
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#define CLKID_AO_32K_PRE 12
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#define CLKID_AO_32K_DIV 13
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#define CLKID_AO_32K_SEL 14
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#define CLKID_AO_32K 15
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#define CLKID_AO_CTS_RTC_OSCIN 16
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#endif
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@ -1,36 +0,0 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (c) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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*/
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#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
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#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
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#define CLKID_AO_AHB 0
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#define CLKID_AO_IR_IN 1
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#define CLKID_AO_I2C_M0 2
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#define CLKID_AO_I2C_S0 3
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#define CLKID_AO_UART 4
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#define CLKID_AO_PROD_I2C 5
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#define CLKID_AO_UART2 6
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#define CLKID_AO_IR_OUT 7
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#define CLKID_AO_SAR_ADC 8
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#define CLKID_AO_MAILBOX 9
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#define CLKID_AO_M3 10
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#define CLKID_AO_AHB_SRAM 11
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#define CLKID_AO_RTI 12
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#define CLKID_AO_M4_FCLK 13
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#define CLKID_AO_M4_HCLK 14
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#define CLKID_AO_CLK81 15
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#define CLKID_AO_SAR_ADC_SEL 16
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#define CLKID_AO_SAR_ADC_CLK 18
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#define CLKID_AO_CTS_OSCIN 19
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#define CLKID_AO_32K 23
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#define CLKID_AO_CEC 27
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#define CLKID_AO_CTS_RTC_OSCIN 28
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#endif
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/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
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/*
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* Meson-G12A clock tree IDs
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*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __G12A_CLKC_H
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#define __G12A_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_GP0_PLL 7
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#define CLKID_CLK81 10
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#define CLKID_MPLL0 11
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#define CLKID_MPLL1 12
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#define CLKID_MPLL2 13
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#define CLKID_MPLL3 14
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#define CLKID_DDR 15
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#define CLKID_DOS 16
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#define CLKID_AUDIO_LOCKER 17
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#define CLKID_MIPI_DSI_HOST 18
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#define CLKID_ETH_PHY 19
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#define CLKID_ISA 20
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#define CLKID_PL301 21
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#define CLKID_PERIPHS 22
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#define CLKID_SPICC0 23
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#define CLKID_I2C 24
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#define CLKID_SANA 25
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#define CLKID_SD 26
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#define CLKID_RNG0 27
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#define CLKID_UART0 28
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#define CLKID_SPICC1 29
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#define CLKID_HIU_IFACE 30
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#define CLKID_MIPI_DSI_PHY 31
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#define CLKID_ASSIST_MISC 32
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#define CLKID_SD_EMMC_A 33
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#define CLKID_SD_EMMC_B 34
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#define CLKID_SD_EMMC_C 35
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#define CLKID_AUDIO_CODEC 36
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#define CLKID_AUDIO 37
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#define CLKID_ETH 38
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#define CLKID_DEMUX 39
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#define CLKID_AUDIO_IFIFO 40
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#define CLKID_ADC 41
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#define CLKID_UART1 42
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#define CLKID_G2D 43
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#define CLKID_RESET 44
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#define CLKID_PCIE_COMB 45
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#define CLKID_PARSER 46
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#define CLKID_USB 47
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#define CLKID_PCIE_PHY 48
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#define CLKID_AHB_ARB0 49
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#define CLKID_AHB_DATA_BUS 50
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#define CLKID_AHB_CTRL_BUS 51
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#define CLKID_HTX_HDCP22 52
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#define CLKID_HTX_PCLK 53
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#define CLKID_BT656 54
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#define CLKID_USB1_DDR_BRIDGE 55
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#define CLKID_MMC_PCLK 56
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#define CLKID_UART2 57
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#define CLKID_VPU_INTR 58
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#define CLKID_GIC 59
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#define CLKID_SD_EMMC_A_CLK0 60
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#define CLKID_SD_EMMC_B_CLK0 61
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#define CLKID_SD_EMMC_C_CLK0 62
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#define CLKID_HIFI_PLL 74
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#define CLKID_VCLK2_VENCI0 80
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#define CLKID_VCLK2_VENCI1 81
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#define CLKID_VCLK2_VENCP0 82
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#define CLKID_VCLK2_VENCP1 83
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#define CLKID_VCLK2_VENCT0 84
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#define CLKID_VCLK2_VENCT1 85
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#define CLKID_VCLK2_OTHER 86
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#define CLKID_VCLK2_ENCI 87
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#define CLKID_VCLK2_ENCP 88
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#define CLKID_DAC_CLK 89
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#define CLKID_AOCLK 90
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#define CLKID_IEC958 91
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#define CLKID_ENC480P 92
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#define CLKID_RNG1 93
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#define CLKID_VCLK2_ENCT 94
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#define CLKID_VCLK2_ENCL 95
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#define CLKID_VCLK2_VENCLMMC 96
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#define CLKID_VCLK2_VENCL 97
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#define CLKID_VCLK2_OTHER1 98
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#define CLKID_FCLK_DIV2P5 99
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#define CLKID_DMA 105
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#define CLKID_EFUSE 106
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#define CLKID_ROM_BOOT 107
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#define CLKID_RESET_SEC 108
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#define CLKID_SEC_AHB_APB3 109
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#define CLKID_VPU_0_SEL 110
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#define CLKID_VPU_0 112
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#define CLKID_VPU_1_SEL 113
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#define CLKID_VPU_1 115
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#define CLKID_VPU 116
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#define CLKID_VAPB_0_SEL 117
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#define CLKID_VAPB_0 119
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#define CLKID_VAPB_1_SEL 120
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#define CLKID_VAPB_1 122
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#define CLKID_VAPB_SEL 123
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#define CLKID_VAPB 124
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#define CLKID_HDMI_PLL 128
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#define CLKID_VID_PLL 129
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#define CLKID_VCLK 138
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#define CLKID_VCLK2 139
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#define CLKID_VCLK_DIV1 148
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#define CLKID_VCLK_DIV2 149
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#define CLKID_VCLK_DIV4 150
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#define CLKID_VCLK_DIV6 151
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#define CLKID_VCLK_DIV12 152
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#define CLKID_VCLK2_DIV1 153
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#define CLKID_VCLK2_DIV2 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6 156
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#define CLKID_VCLK2_DIV12 157
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#define CLKID_CTS_ENCI 162
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#define CLKID_CTS_ENCP 163
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#define CLKID_CTS_VDAC 164
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#define CLKID_HDMI_TX 165
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#define CLKID_HDMI 168
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#define CLKID_MALI_0_SEL 169
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#define CLKID_MALI_0 171
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#define CLKID_MALI_1_SEL 172
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#define CLKID_MALI_1 174
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#define CLKID_MALI 175
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#define CLKID_MPLL_50M 177
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#define CLKID_CPU_CLK 187
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#define CLKID_PCIE_PLL 201
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#define CLKID_VDEC_1 204
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#define CLKID_VDEC_HEVC 207
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#define CLKID_VDEC_HEVCF 210
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#define CLKID_TS 212
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#define CLKID_CPUB_CLK 224
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#define CLKID_GP1_PLL 243
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#define CLKID_DSU_CLK 252
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#define CLKID_CPU1_CLK 253
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#define CLKID_CPU2_CLK 254
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#define CLKID_CPU3_CLK 255
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#define CLKID_SPICC0_SCLK 258
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#define CLKID_SPICC1_SCLK 261
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#define CLKID_NNA_AXI_CLK 264
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#define CLKID_NNA_CORE_CLK 267
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#define CLKID_MIPI_DSI_PXCLK_SEL 269
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#define CLKID_MIPI_DSI_PXCLK 270
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#endif /* __G12A_CLKC_H */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
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#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
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#define CLKID_AO_REMOTE 0
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#define CLKID_AO_I2C_MASTER 1
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#define CLKID_AO_I2C_SLAVE 2
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#define CLKID_AO_UART1 3
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#define CLKID_AO_UART2 4
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#define CLKID_AO_IR_BLASTER 5
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#define CLKID_AO_CEC_32K 6
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#define CLKID_AO_CTS_OSCIN 7
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#define CLKID_AO_32K_PRE 8
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#define CLKID_AO_32K_DIV 9
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#define CLKID_AO_32K_SEL 10
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#define CLKID_AO_32K 11
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#define CLKID_AO_CTS_RTC_OSCIN 12
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#define CLKID_AO_CLK81 13
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#endif
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@ -1,151 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* GXBB clock tree IDs
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*/
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_HDMI_PLL 2
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#define CLKID_FIXED_PLL 3
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#define CLKID_FCLK_DIV2 4
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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#define CLKID_GP0_PLL 9
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#define CLKID_CLK81 12
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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#define CLKID_MPLL2 15
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_SMART_CARD 24
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#define CLKID_RNG0 25
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#define CLKID_UART0 26
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_I2S_SPDIF 35
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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#define CLKID_MIXER_IFACE 44
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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#define CLKID_USB 55
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_AO_I2C 93
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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||||
#define CLKID_SAR_ADC_CLK 97
|
||||
#define CLKID_SAR_ADC_SEL 98
|
||||
#define CLKID_MALI_0_SEL 100
|
||||
#define CLKID_MALI_0 102
|
||||
#define CLKID_MALI_1_SEL 103
|
||||
#define CLKID_MALI_1 105
|
||||
#define CLKID_MALI 106
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_I958 113
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_SD_EMMC_A_CLK0 119
|
||||
#define CLKID_SD_EMMC_B_CLK0 122
|
||||
#define CLKID_SD_EMMC_C_CLK0 125
|
||||
#define CLKID_VPU_0_SEL 126
|
||||
#define CLKID_VPU_0 128
|
||||
#define CLKID_VPU_1_SEL 129
|
||||
#define CLKID_VPU_1 131
|
||||
#define CLKID_VPU 132
|
||||
#define CLKID_VAPB_0_SEL 133
|
||||
#define CLKID_VAPB_0 135
|
||||
#define CLKID_VAPB_1_SEL 136
|
||||
#define CLKID_VAPB_1 138
|
||||
#define CLKID_VAPB_SEL 139
|
||||
#define CLKID_VAPB 140
|
||||
#define CLKID_VDEC_1 153
|
||||
#define CLKID_VDEC_HEVC 156
|
||||
#define CLKID_GEN_CLK 159
|
||||
#define CLKID_VID_PLL 166
|
||||
#define CLKID_VCLK 175
|
||||
#define CLKID_VCLK2 176
|
||||
#define CLKID_VCLK_DIV1 185
|
||||
#define CLKID_VCLK_DIV2 186
|
||||
#define CLKID_VCLK_DIV4 187
|
||||
#define CLKID_VCLK_DIV6 188
|
||||
#define CLKID_VCLK_DIV12 189
|
||||
#define CLKID_VCLK2_DIV1 190
|
||||
#define CLKID_VCLK2_DIV2 191
|
||||
#define CLKID_VCLK2_DIV4 192
|
||||
#define CLKID_VCLK2_DIV6 193
|
||||
#define CLKID_VCLK2_DIV12 194
|
||||
#define CLKID_CTS_ENCI 199
|
||||
#define CLKID_CTS_ENCP 200
|
||||
#define CLKID_CTS_VDAC 201
|
||||
#define CLKID_HDMI_TX 202
|
||||
#define CLKID_HDMI 205
|
||||
#define CLKID_ACODEC 206
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2018 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
|
||||
|
||||
#define RESET_AO_REMOTE 0
|
||||
#define RESET_AO_I2C_MASTER 1
|
||||
#define RESET_AO_I2C_SLAVE 2
|
||||
#define RESET_AO_UART1 3
|
||||
#define RESET_AO_UART2 4
|
||||
#define RESET_AO_IR_BLASTER 5
|
||||
|
||||
#endif
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
|
||||
|
||||
#define RESET_AO_IR_IN 0
|
||||
#define RESET_AO_UART 1
|
||||
#define RESET_AO_I2C_M 2
|
||||
#define RESET_AO_I2C_S 3
|
||||
#define RESET_AO_SAR_ADC 4
|
||||
#define RESET_AO_UART2 5
|
||||
#define RESET_AO_IR_OUT 6
|
||||
|
||||
#endif
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
/*
|
||||
* This file is provided under a dual BSD/GPLv2 license. When using or
|
||||
* redistributing this file, you may do so under either license.
|
||||
*
|
||||
* GPL LICENSE SUMMARY
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
* The full GNU General Public License is included in this distribution
|
||||
* in the file called COPYING.
|
||||
*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright (c) 2016 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Intel Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
|
||||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
|
||||
|
||||
#define RESET_AO_REMOTE 0
|
||||
#define RESET_AO_I2C_MASTER 1
|
||||
#define RESET_AO_I2C_SLAVE 2
|
||||
#define RESET_AO_UART1 3
|
||||
#define RESET_AO_UART2 4
|
||||
#define RESET_AO_IR_BLASTER 5
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue