powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes

Print fpga info at last_stage_init on gdsys 405ep boards.
Use dtt_init() to startup fans.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

board/gdsys/405ep/dlvision-10g.c

@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
 
 #include "405ep.h"
 #include <gdsys_fpga.h>
@@ -68,6 +69,14 @@ enum {
 	RAM_DDR2_64 = 2,
 };
 
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
 static unsigned int get_hwver(void)
 {
 	u16 latch3 = in_le16((void *)LATCH3_BASE);
@@ -226,24 +235,19 @@ static void print_fpga_info(unsigned dev)
  */
 int checkboard(void)
 {
-	char buf[64];
+	char *s = getenv("serial#");
-	int i = getenv_f("serial#", buf, sizeof(buf));
 
-	printf("Board: ");
+	puts("Board: ");
 
-	printf("DLVision 10G");
+	puts("DLVision 10G");
 
-	if (i > 0) {
+	if (s != NULL) {
 		puts(", serial# ");
-		puts(buf);
+		puts(s);
 	}
 
 	puts("\n");
 
-	print_fpga_info(0);
-	if (get_mc2_present())
-		print_fpga_info(1);
-
 	return 0;
 }
 
@@ -252,6 +256,10 @@ int last_stage_init(void)
 	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 
+	print_fpga_info(0);
+	if (get_mc2_present())
+		print_fpga_info(1);
+
 	if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 		return 0;
 

board/gdsys/405ep/io.c

@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+#include <dtt.h>
 #include <miiphy.h>
 
 #include "405ep.h"
@@ -52,6 +53,14 @@ enum {
 	HWVER_122 = 3,
 };
 
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
 int configure_gbit_phy(unsigned char addr)
 {
 	unsigned short value;
@@ -92,8 +101,22 @@ err_out:
  */
 int checkboard(void)
 {
-	char buf[64];
+	char *s = getenv("serial#");
-	int i = getenv_f("serial#", buf, sizeof(buf));
+
+	puts("Board: CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
 	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
@@ -108,15 +131,7 @@ int checkboard(void)
 	feature_channels = fpga_features & 0x007f;
 	feature_expansion = fpga_features & (1<<15);
 
-	printf("Board: ");
+	puts("FPGA:  ");
-
-	printf("CATCenter Io");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
 
 	switch (unit_type) {
 	case UNITTYPE_CCD_SWITCH:
@@ -157,8 +172,6 @@ int checkboard(void)
 	printf(" %d channel(s)", feature_channels);
 
 	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
-	return 0;
 }
 
 /*
@@ -169,6 +182,8 @@ int last_stage_init(void)
 	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
+	print_fpga_info();
+
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
 		bb_miiphy_read, bb_miiphy_write);
 

board/gdsys/405ep/iocon.c

@@ -74,8 +74,24 @@ enum {
  */
 int checkboard(void)
 {
-	char buf[64];
+	char *s = getenv("serial#");
-	int i = getenv_f("serial#", buf, sizeof(buf));
+
+	puts("Board: ");
+
+	puts("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
 	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
@@ -100,16 +116,6 @@ int checkboard(void)
 	feature_carriers = (fpga_features & 0x000c) >> 2;
 	feature_video_channels = fpga_features & 0x0003;
 
-	printf("Board: ");
-
-	printf("IoCon");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
-
 	switch (unit_type) {
 	case UNITTYPE_MAIN_USER:
 		printf("Mainchannel");
@@ -210,12 +216,12 @@ int checkboard(void)
 	printf(", %d carrier(s)", feature_carriers);
 
 	printf(", %d video channel(s)\n", feature_video_channels);
-
-	return 0;
 }
 
 int last_stage_init(void)
 {
+	print_fpga_info();
+
 	return osd_probe(0);
 }
 

include/configs/dlvision-10g.h

@@ -39,6 +39,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
@@ -81,6 +82,7 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 
 /*

include/configs/io.h

@@ -39,6 +39,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
@@ -77,6 +78,7 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 
 /*