Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-22 04:44:46 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

Browse source 
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23080

- board: migrate PolarFire to use OF_UPSTREAM
- dts: align DT with QEMU amd-microblaze-v-virt platform
- riscv: fix resume utility
This commit is contained in:
Tom Rini 2024-10-29 07:36:48 -06:00
commit b1967f66f8
18 changed files with 115 additions and 884 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/riscv/dts/Makefile
View file

@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb

71
arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
View file

@ -1,71 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <3>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
status = "disabled";
};
i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
reg = <0x0 0x40000200 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
interrupt-parent = <&plic>;
interrupts = <122>;
clock-frequency = <100000>;
status = "disabled";
};
pcie: pcie@3000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
clock-names = "fic1", "fic3";
ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
msi-parent = <&pcie>;
msi-controller;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
refclk_ccc: cccrefclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
&ccc_nw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
"dll0_ref", "dll1_ref";
status = "okay";
};

14
arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi
View file

@ -1,14 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2020 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
/ {
aliases {
cpu1 = &cpu1;
cpu2 = &cpu2;
cpu3 = &cpu3;
cpu4 = &cpu4;
};
};

208
arch/riscv/dts/mpfs-icicle-kit.dts
View file

@ -1,208 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led1";
};
led-2 {
gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led2";
};
led-3 {
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led3";
};
led-4 {
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led4";
};
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
status = "okay";
};
ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss_payload: region@BFC00000 {
reg = <0x0 0xBFC00000 0x0 0x400000>;
no-map;
};
};
};
&core_pwm0 {
status = "okay";
};
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "enabled";
};
&mac1 {
phy-mode = "sgmii";
phy-handle = <&phy1>;
status = "okay";
phy1: ethernet-phy@9 {
reg = <9>;
};
phy0: ethernet-phy@8 {
reg = <8>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&pcie {
status = "okay";
};
&qspi {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&refclk_ccc {
clock-frequency = <50000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&syscontroller {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "host";
};

511
arch/riscv/dts/mpfs.dtsi
View file

@ -1,511 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#include "dt-bindings/clock/microchip-mpfs-clock.h"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
};
};
};
refclk: mssrefclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
cctrllr: cache-controller@2010000 {
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <3>, <4>, <2>;
};
clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};
pdma: dma-controller@3000000 {
compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
dma-channels = <4>;
#dma-cells = <1>;
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ccc_se: clock-controller@38010000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
<0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_ne: clock-controller@38040000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
<0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_nw: clock-controller@38100000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
<0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_sw: clock-controller@38400000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
<0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
status = "disabled"; /* Reserved for the HSS */
};
mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
mmuart4: serial@20106000 {
compatible = "ns16550a";
reg = <0x0 0x20106000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <94>;
clocks = <&clkcfg CLK_MMUART4>;
current-speed = <115200>;
status = "disabled";
};
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
spi0: spi@20108000 {
compatible = "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20108000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <54>;
clocks = <&clkcfg CLK_SPI0>;
status = "disabled";
};
spi1: spi@20109000 {
compatible = "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20109000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <55>;
clocks = <&clkcfg CLK_SPI1>;
status = "disabled";
};
qspi: spi@21000000 {
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21000000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <85>;
clocks = <&clkcfg CLK_QSPI>;
status = "disabled";
};
i2c0: i2c@2010a000 {
compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010a000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clkcfg CLK_I2C0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@2010b000 {
compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010b000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <61>;
clocks = <&clkcfg CLK_I2C1>;
clock-frequency = <100000>;
status = "disabled";
};
can0: can@2010c000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010c000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN0>;
interrupt-parent = <&plic>;
interrupts = <56>;
status = "disabled";
};
can1: can@2010d000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010d000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN1>;
interrupt-parent = <&plic>;
interrupts = <57>;
status = "disabled";
};
mac0: ethernet@20110000 {
compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC0>;
status = "disabled";
};
mac1: ethernet@20112000 {
compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC1>;
status = "disabled";
};
gpio0: gpio@20120000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x0 0x20124000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <80>, <81>;
clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
clock-names = "rtc", "rtcref";
status = "disabled";
};
usb: usb@20201000 {
compatible = "microchip,mpfs-musb";
reg = <0x0 0x20201000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <86>, <87>;
clocks = <&clkcfg CLK_USB>;
interrupt-names = "dma","mc";
status = "disabled";
};
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
<0x0 0x37020800 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;
status = "disabled";
};
};
};

30
arch/riscv/dts/xilinx-mbv32.dts
View file

@ -20,7 +20,7 @@
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <102000000>;
timebase-frequency = <100000000>;
cpu_0: cpu@0 {
compatible = "amd,mbv32", "riscv";
device_type = "cpu";
@ -28,7 +28,7 @@
riscv,isa = "rv32imafdc";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <102000000>;
clock-frequency = <100000000>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
@ -46,15 +46,15 @@
stdout-path = "serial0:115200n8";
};
memory@20000000 {
memory@80000000 {
device_type = "memory";
reg = <0x20000000 0x20000000>;
reg = <0x80000000 0x40000000>;
};
clk102: clock {
clk100: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <102000000>;
clock-frequency = <100000000>;
};
axi: axi {
@ -77,30 +77,20 @@
compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c00000 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <1 2>;
interrupts = <0 2>;
bootph-all;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk102>;
};
xlnx_timer1: timer@41c20000 {
compatible = "xlnx,xps-timer-1.00.a";
reg = <0x41c20000 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk102>;
clocks = <&clk100>;
};
uart0: serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0x40600000 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <2 2>;
interrupts = <1 2>;
bootph-all;
clocks = <&clk102>;
clocks = <&clk100>;
current-speed = <115200>;
xlnx,data-bits = <8>;
xlnx,use-parity = <0>;

1
arch/riscv/include/asm/global_data.h
View file

@ -42,6 +42,7 @@ struct arch_global_data {
#ifdef CONFIG_SMBIOS
ulong smbios_start; /* Start address of SMBIOS table */
#endif
struct resume_data *resume;
};
#include <asm-generic/global_data.h>

10
arch/riscv/lib/interrupts.c
View file

@ -22,11 +22,9 @@
DECLARE_GLOBAL_DATA_PTR;
static struct resume_data *resume;
void set_resume(struct resume_data *data)
{
resume = data;
gd->arch.resume = data;
}
static void show_efi_loaded_images(uintptr_t epc)
@ -138,9 +136,9 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
"Store/AMO page fault",
};
if (resume) {
resume->code = code;
longjmp(resume->jump, 1);
if (gd->arch.resume) {
gd->arch.resume->code = code;
longjmp(gd->arch.resume->jump, 1);
}
if (code < ARRAY_SIZE(exception_code))

2
board/microchip/mpfs_icicle/Kconfig
View file

@ -24,6 +24,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply SMP
imply CLK_CCF
imply CLK_MPFS
imply REGMAP
imply SYSCON
imply SYS_NS16550
imply CMD_DHCP
imply CMD_EXT2

6
board/xilinx/mbv/Kconfig
View file

@ -10,14 +10,14 @@ config SYS_CPU
default "generic"
config TEXT_BASE
default 0x21200000
default 0x81200000
config SPL_TEXT_BASE
default 0x20000000
default 0x80000000
config SPL_OPENSBI_LOAD_ADDR
hex
default 0x20200000
default 0x80200000
config BOARD_SPECIFIC_OPTIONS
def_bool y

4
configs/microchip_mpfs_icicle_defconfig
View file

@ -4,8 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit"
CONFIG_OF_UPSTREAM=y
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SYS_MEM_TOP_HIDE=0x400000
CONFIG_TARGET_MICROCHIP_ICICLE=y

12
configs/xilinx_mbv32_defconfig
View file

@ -2,17 +2,17 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
CONFIG_SPL_STACK=0x20200000
CONFIG_SPL_BSS_START_ADDR=0x24000000
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y
@ -20,7 +20,7 @@ CONFIG_TARGET_XILINX_MBV=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y

2
drivers/clk/microchip/Kconfig
View file

@ -1,5 +1,7 @@
config CLK_MPFS
bool "Clock support for Microchip PolarFire SoC"
depends on CLK && CLK_CCF
depends on SYSCON
depends on REGMAP
help
This enables support clock driver for Microchip PolarFire SoC platform.

63
drivers/clk/microchip/mpfs_clk.c
View file

@ -9,25 +9,39 @@
#include <log.h>
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/ofnode.h>
#include <dm/uclass.h>
#include <regmap.h>
#include <syscon.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
#include "mpfs_clk.h"
static int mpfs_clk_probe(struct udevice *dev)
static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base,
struct regmap **regmap)
{
ofnode node;
node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg");
if (!ofnode_valid(node))
return -ENODEV;
*regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
*msspll_base = dev_read_addr_index_ptr(dev, 0);
return 0;
}
static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base,
struct regmap **regmap)
{
struct clk *parent_clk = dev_get_priv(dev);
struct clk clk_msspll = { .id = CLK_MSSPLL };
void __iomem *base;
void __iomem *msspll_base;
int ret;
base = dev_read_addr_index_ptr(dev, 0);
if (!base)
return -EINVAL;
ret = clk_get_by_index(dev, 0, parent_clk);
ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0);
if (ret)
return ret;
@ -40,7 +54,30 @@ static int mpfs_clk_probe(struct udevice *dev)
* Otherwise, skip registering it & pass the reference clock directly
* to the cfg clock registration function.
*/
msspll_base = dev_read_addr_index_ptr(dev, 1);
*msspll_base = dev_read_addr_index_ptr(dev, 1);
return 0;
}
static int mpfs_clk_probe(struct udevice *dev)
{
struct clk *parent_clk = dev_get_priv(dev);
struct clk clk_msspll = { .id = CLK_MSSPLL };
struct regmap *regmap;
void __iomem *msspll_base;
int ret;
ret = clk_get_by_index(dev, 0, parent_clk);
if (ret)
return ret;
ret = mpfs_clk_syscon_probe(dev, &msspll_base, &regmap);
if (ret) {
ret = mpfs_clk_old_format_probe(dev, &msspll_base, &regmap);
if (ret)
return ret;
}
if (msspll_base) {
ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
if (ret)
@ -50,11 +87,11 @@ static int mpfs_clk_probe(struct udevice *dev)
parent_clk = &clk_msspll;
}
ret = mpfs_clk_register_cfgs(base, parent_clk);
ret = mpfs_clk_register_cfgs(parent_clk, regmap);
if (ret)
return ret;
ret = mpfs_clk_register_periphs(base, dev);
ret = mpfs_clk_register_periphs(dev, regmap);
return ret;
}

5
drivers/clk/microchip/mpfs_clk.h
View file

@ -7,6 +7,7 @@
#define __MICROCHIP_MPFS_CLK_H
#include <linux/clk-provider.h>
#include <regmap.h>
/**
* mpfs_clk_register_cfgs() - register configuration clocks
*
@ -14,7 +15,7 @@
* @parent: a pointer to parent clock.
* Return: zero on success, or a negative error code.
*/
int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap);
/**
* mpfs_clk_register_msspll() - register the mss pll
*
@ -30,7 +31,7 @@ int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
* @dev: udevice representing the clock controller.
* Return: zero on success, or a negative error code.
*/
int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap);
/**
* divider_get_val() - get the clock divider value
*

16
drivers/clk/microchip/mpfs_clk_cfg.c
View file

@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@ -57,7 +58,7 @@ struct mpfs_cfg_clock {
*/
struct mpfs_cfg_hw_clock {
struct mpfs_cfg_clock cfg;
void __iomem *sys_base;
struct regmap *regmap;
u32 prate;
struct clk hw;
};
@ -68,11 +69,11 @@ static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw)
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
void __iomem *base_addr = cfg_hw->sys_base;
unsigned long rate;
u32 val;
val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
val >>= cfg->shift;
val &= clk_div_mask(cfg->width);
rate = cfg_hw->prate / (1u << val);
hw->rate = rate;
@ -84,7 +85,6 @@ static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)
{
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
void __iomem *base_addr = cfg_hw->sys_base;
u32 val;
int divider_setting;
@ -93,10 +93,10 @@ static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)
if (divider_setting < 0)
return divider_setting;
val = readl(base_addr + REG_CLOCK_CONFIG_CR);
regmap_read(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, &val);
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
val |= divider_setting << cfg->shift;
writel(val, base_addr + REG_CLOCK_CONFIG_CR);
regmap_write(cfg_hw->regmap, REG_CLOCK_CONFIG_CR, val);
return clk_get_rate(hw);
}
@ -116,7 +116,7 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
};
int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@ -126,7 +126,7 @@ int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
num_clks = ARRAY_SIZE(mpfs_cfg_clks);
for (i = 0; i < num_clks; i++) {
hw = &mpfs_cfg_clks[i].hw;
mpfs_cfg_clks[i].sys_base = base;
mpfs_cfg_clks[i].regmap = regmap;
mpfs_cfg_clks[i].prate = clk_get_rate(parent);
name = mpfs_cfg_clks[i].cfg.name;
ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent->dev->name);

37
drivers/clk/microchip/mpfs_clk_periph.c
View file

@ -9,6 +9,7 @@
#include <dm/device.h>
#include <dm/devres.h>
#include <dm/uclass.h>
#include <regmap.h>
#include <dt-bindings/clock/microchip-mpfs-clock.h>
#include <linux/err.h>
@ -50,7 +51,7 @@ struct mpfs_periph_clock {
*/
struct mpfs_periph_hw_clock {
struct mpfs_periph_clock periph;
void __iomem *sys_base;
struct regmap *regmap;
u32 prate;
struct clk hw;
};
@ -61,17 +62,16 @@ static int mpfs_periph_clk_enable(struct clk *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
void __iomem *base_addr = periph_hw->sys_base;
u32 reg, val;
u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
reg = readl(base_addr + REG_SUBBLK_RESET_CR);
val = reg & ~(1u << periph->shift);
writel(val, base_addr + REG_SUBBLK_RESET_CR);
regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, &reg);
reg &= ~(1u << periph->shift);
regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
val = reg | (1u << periph->shift);
writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, &reg);
reg |= (1u << periph->shift);
regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@ -81,17 +81,16 @@ static int mpfs_periph_clk_disable(struct clk *hw)
{
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
struct mpfs_periph_clock *periph = &periph_hw->periph;
void __iomem *base_addr = periph_hw->sys_base;
u32 reg, val;
u32 reg;
if (periph->flags != CLK_IS_CRITICAL) {
reg = readl(base_addr + REG_SUBBLK_RESET_CR);
val = reg | (1u << periph->shift);
writel(val, base_addr + REG_SUBBLK_RESET_CR);
regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, &reg);
reg |= (1u << periph->shift);
regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
val = reg & ~(1u << periph->shift);
writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, &reg);
reg &= ~(1u << periph->shift);
regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
}
return 0;
@ -159,7 +158,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
};
int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev)
int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap)
{
int ret;
int i, id, num_clks;
@ -172,7 +171,7 @@ int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev)
clk_request(dev, &parent);
hw = &mpfs_periph_clks[i].hw;
mpfs_periph_clks[i].sys_base = base;
mpfs_periph_clks[i].regmap = regmap;
mpfs_periph_clks[i].prate = clk_get_rate(&parent);
name = mpfs_periph_clks[i].periph.name;
ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name);

6
dts/upstream/src/riscv/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
include $(srctree)/scripts/Makefile.dts
DTC_FLAGS += -R 4 -p 0x1000