mirror of
https://github.com/u-boot/u-boot.git
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i2c: fti2c010: remove unused/unmaintained driver
CONFIG_SYS_I2C_FTI2C010 is not enabled by anyone.
Commit 2852709676 ("dm: i2c: Add a note to I2C drivers which need
conversion") prompted to convert this driver to DM before June 2017,
but not converted yet.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
1d14cbdcd8
commit
af6715bfb4
3 changed files with 0 additions and 421 deletions
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@ -20,7 +20,6 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
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obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
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obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
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obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
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obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
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obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
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obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
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@ -1,340 +0,0 @@
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/*
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* Faraday I2C Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* NOTE: This driver should be converted to driver model before June 2017.
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* Please see doc/driver-model/i2c-howto.txt for instructions.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include "fti2c010.h"
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#ifndef CONFIG_SYS_I2C_SPEED
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#define CONFIG_SYS_I2C_SPEED 5000
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#endif
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#ifndef CONFIG_SYS_I2C_SLAVE
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#define CONFIG_SYS_I2C_SLAVE 0
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#endif
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#ifndef CONFIG_FTI2C010_CLOCK
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#define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
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#endif
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#ifndef CONFIG_FTI2C010_TIMEOUT
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#define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
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#endif
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/* 7-bit dev address + 1-bit read/write */
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#define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
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#define I2C_WR(dev) (((dev) << 1) & 0xfe)
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struct fti2c010_chip {
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struct fti2c010_regs *regs;
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};
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static struct fti2c010_chip chip_list[] = {
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{
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE,
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},
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#ifdef CONFIG_FTI2C010_BASE1
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{
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE1,
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},
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#endif
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#ifdef CONFIG_FTI2C010_BASE2
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{
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE2,
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},
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#endif
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#ifdef CONFIG_FTI2C010_BASE3
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{
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.regs = (struct fti2c010_regs *)CONFIG_FTI2C010_BASE3,
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},
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#endif
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};
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static int fti2c010_reset(struct fti2c010_chip *chip)
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{
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ulong ts;
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int ret = -1;
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struct fti2c010_regs *regs = chip->regs;
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writel(CR_I2CRST, ®s->cr);
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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if (!(readl(®s->cr) & CR_I2CRST)) {
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ret = 0;
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break;
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}
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}
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if (ret)
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printf("fti2c010: reset timeout\n");
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return ret;
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}
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static int fti2c010_wait(struct fti2c010_chip *chip, uint32_t mask)
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{
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int ret = -1;
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uint32_t stat, ts;
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struct fti2c010_regs *regs = chip->regs;
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for (ts = get_timer(0); get_timer(ts) < CONFIG_FTI2C010_TIMEOUT; ) {
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stat = readl(®s->sr);
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if ((stat & mask) == mask) {
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ret = 0;
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break;
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}
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}
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return ret;
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}
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static unsigned int set_i2c_bus_speed(struct fti2c010_chip *chip,
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unsigned int speed)
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{
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struct fti2c010_regs *regs = chip->regs;
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unsigned int clk = CONFIG_FTI2C010_CLOCK;
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unsigned int gsr = 0;
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unsigned int tsr = 32;
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unsigned int div, rate;
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for (div = 0; div < 0x3ffff; ++div) {
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/* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
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rate = clk / (2 * (div + 2) + gsr);
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if (rate <= speed)
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break;
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}
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writel(TGSR_GSR(gsr) | TGSR_TSR(tsr), ®s->tgsr);
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writel(CDR_DIV(div), ®s->cdr);
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return rate;
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}
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/*
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* Initialization, must be called once on start up, may be called
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* repeatedly to change the speed and slave addresses.
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*/
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static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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if (adap->init_done)
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return;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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/* master init */
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fti2c010_reset(chip);
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set_i2c_bus_speed(chip, speed);
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/* slave init, don't care */
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}
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/*
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* Probe the given I2C chip address. Returns 0 if a chip responded,
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* not 0 on failure.
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*/
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static int fti2c010_probe(struct i2c_adapter *adap, u8 dev)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret;
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/* 1. Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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/* 2. Select device register */
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writel(0, ®s->dr);
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writel(CR_ENABLE | CR_TBEN, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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return ret;
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}
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static void to_i2c_addr(u8 *buf, uint32_t addr, int alen)
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{
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int i, shift;
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if (!buf || alen <= 0)
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return;
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/* MSB first */
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i = 0;
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shift = (alen - 1) * 8;
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while (alen-- > 0) {
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buf[i] = (u8)(addr >> shift);
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shift -= 8;
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}
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}
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static int fti2c010_read(struct i2c_adapter *adap,
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u8 dev, uint addr, int alen, uchar *buf, int len)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret, pos;
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uchar paddr[4] = { 0 };
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to_i2c_addr(paddr, addr, alen);
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/*
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* Phase A. Set register address
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*/
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/* A.1 Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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/* A.2 Select device register */
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for (pos = 0; pos < alen; ++pos) {
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uint32_t ctrl = CR_ENABLE | CR_TBEN;
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writel(paddr[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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}
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/*
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* Phase B. Get register data
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*/
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/* B.1 Select slave device (7bits Address + 1bit R/W) */
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writel(I2C_RD(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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/* B.2 Get register data */
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for (pos = 0; pos < len; ++pos) {
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uint32_t ctrl = CR_ENABLE | CR_TBEN;
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uint32_t stat = SR_DR;
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if (pos == len - 1) {
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ctrl |= CR_NAK | CR_STOP;
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stat |= SR_ACK;
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}
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(chip, stat);
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if (ret)
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break;
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buf[pos] = (uchar)(readl(®s->dr) & 0xFF);
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}
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return ret;
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}
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static int fti2c010_write(struct i2c_adapter *adap,
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u8 dev, uint addr, int alen, u8 *buf, int len)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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struct fti2c010_regs *regs = chip->regs;
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int ret, pos;
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uchar paddr[4] = { 0 };
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to_i2c_addr(paddr, addr, alen);
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/*
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* Phase A. Set register address
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*
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* A.1 Select slave device (7bits Address + 1bit R/W)
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*/
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writel(I2C_WR(dev), ®s->dr);
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writel(CR_ENABLE | CR_TBEN | CR_START, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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/* A.2 Select device register */
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for (pos = 0; pos < alen; ++pos) {
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uint32_t ctrl = CR_ENABLE | CR_TBEN;
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writel(paddr[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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return ret;
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}
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/*
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* Phase B. Set register data
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*/
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for (pos = 0; pos < len; ++pos) {
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uint32_t ctrl = CR_ENABLE | CR_TBEN;
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if (pos == len - 1)
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ctrl |= CR_STOP;
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writel(buf[pos], ®s->dr);
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writel(ctrl, ®s->cr);
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ret = fti2c010_wait(chip, SR_DT);
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if (ret)
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break;
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}
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return ret;
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}
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static unsigned int fti2c010_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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struct fti2c010_chip *chip = chip_list + adap->hwadapnr;
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int ret;
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fti2c010_reset(chip);
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ret = set_i2c_bus_speed(chip, speed);
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return ret;
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}
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/*
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* Register i2c adapters
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*/
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U_BOOT_I2C_ADAP_COMPLETE(i2c_0, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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0)
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#ifdef CONFIG_FTI2C010_BASE1
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U_BOOT_I2C_ADAP_COMPLETE(i2c_1, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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1)
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#endif
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#ifdef CONFIG_FTI2C010_BASE2
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U_BOOT_I2C_ADAP_COMPLETE(i2c_2, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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2)
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#endif
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#ifdef CONFIG_FTI2C010_BASE3
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U_BOOT_I2C_ADAP_COMPLETE(i2c_3, fti2c010_init, fti2c010_probe, fti2c010_read,
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fti2c010_write, fti2c010_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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3)
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#endif
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@ -1,80 +0,0 @@
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/*
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* Faraday I2C Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FTI2C010_H
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#define __FTI2C010_H
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/*
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* FTI2C010 registers
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*/
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struct fti2c010_regs {
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uint32_t cr; /* 0x00: control register */
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uint32_t sr; /* 0x04: status register */
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uint32_t cdr; /* 0x08: clock division register */
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uint32_t dr; /* 0x0c: data register */
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uint32_t sar; /* 0x10: slave address register */
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uint32_t tgsr;/* 0x14: time & glitch suppression register */
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uint32_t bmr; /* 0x18: bus monitor register */
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uint32_t rsvd[5];
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uint32_t revr;/* 0x30: revision register */
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};
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/*
|
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* control register
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*/
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#define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */
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#define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */
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#define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */
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#define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */
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#define CR_DRIRQ 0x200 /* rx interrupt (both) */
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#define CR_DTIRQ 0x100 /* tx interrupt (both) */
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#define CR_TBEN 0x80 /* tx enable (both) */
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#define CR_NAK 0x40 /* NACK (both) */
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#define CR_STOP 0x20 /* stop (master) */
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#define CR_START 0x10 /* start (master) */
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||||||
#define CR_GCEN 0x8 /* general call support (slave) */
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#define CR_SCLEN 0x4 /* enable clock out (master) */
|
|
||||||
#define CR_I2CEN 0x2 /* enable I2C (both) */
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|
||||||
#define CR_I2CRST 0x1 /* reset I2C (both) */
|
|
||||||
#define CR_ENABLE \
|
|
||||||
(CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* status register
|
|
||||||
*/
|
|
||||||
#define SR_CLRAL 0x400 /* clear arbitration lost */
|
|
||||||
#define SR_CLRGC 0x200 /* clear general call */
|
|
||||||
#define SR_CLRSAM 0x100 /* clear slave address match */
|
|
||||||
#define SR_CLRSTOP 0x80 /* clear stop */
|
|
||||||
#define SR_CLRNAKR 0x40 /* clear NACK respond */
|
|
||||||
#define SR_DR 0x20 /* rx ready */
|
|
||||||
#define SR_DT 0x10 /* tx done */
|
|
||||||
#define SR_BB 0x8 /* bus busy */
|
|
||||||
#define SR_BUSY 0x4 /* chip busy */
|
|
||||||
#define SR_ACK 0x2 /* ACK/NACK received */
|
|
||||||
#define SR_RW 0x1 /* set when master-rx or slave-tx mode */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* clock division register
|
|
||||||
*/
|
|
||||||
#define CDR_DIV(n) ((n) & 0x3ffff)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* time & glitch suppression register
|
|
||||||
*/
|
|
||||||
#define TGSR_GSR(n) (((n) & 0x7) << 10)
|
|
||||||
#define TGSR_TSR(n) ((n) & 0x3ff)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* bus monitor register
|
|
||||||
*/
|
|
||||||
#define BMR_SCL 0x2 /* SCL is pull-up */
|
|
||||||
#define BMR_SDA 0x1 /* SDA is pull-up */
|
|
||||||
|
|
||||||
#endif /* __FTI2C010_H */
|
|
||||||
Loading…
Add table
Reference in a new issue