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riscv: dts: sifive: Synchronize FU740 and Unmatched DT

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These DT files are synchronized from Linux 5.19.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Icenowy Zheng 2022-08-25 16:11:19 +08:00 • committed by Leo Yu-Chi Liang
parent d13cd77068
commit ac48fc3deb
2 changed files with 60 additions and 89 deletions
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69
arch/riscv/dts/fu740-c000.dtsi
View file

@ -1,10 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 SiFive, Inc */ /* Copyright (c) 2020 SiFive, Inc */
/dts-v1/; /dts-v1/;
#include <dt-bindings/clock/sifive-fu740-prci.h> #include <dt-bindings/clock/sifive-fu740-prci.h>
#include <dt-bindings/reset/sifive-fu740-prci.h>
/ { / {
#address-cells = <2>; #address-cells = <2>;
@ -139,20 +138,21 @@
soc { soc {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus"; compatible = "simple-bus";
ranges; ranges;
plic0: interrupt-controller@c000000 { plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0"; #address-cells = <0>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>; reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>; riscv,ndev = <69>;
interrupt-controller; interrupt-controller;
interrupts-extended = < interrupts-extended =
&cpu0_intc 0xffffffff <&cpu0_intc 0xffffffff>,
&cpu1_intc 0xffffffff &cpu1_intc 9 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
&cpu2_intc 0xffffffff &cpu2_intc 9 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
&cpu3_intc 0xffffffff &cpu3_intc 9 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
&cpu4_intc 0xffffffff &cpu4_intc 9>; <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
}; };
prci: clock-controller@10000000 { prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci"; compatible = "sifive,fu740-c000-prci";
@ -203,8 +203,8 @@
}; };
qspi0: spi@10040000 { qspi0: spi@10040000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0"; compatible = "sifive,fu740-c000-spi", "sifive,spi0";
reg = <0x0 0x10040000 0x0 0x1000 reg = <0x0 0x10040000 0x0 0x1000>,
0x0 0x20000000 0x0 0x10000000>; <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <41>; interrupts = <41>;
clocks = <&prci FU740_PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
@ -214,8 +214,8 @@
}; };
qspi1: spi@10041000 { qspi1: spi@10041000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0"; compatible = "sifive,fu740-c000-spi", "sifive,spi0";
reg = <0x0 0x10041000 0x0 0x1000 reg = <0x0 0x10041000 0x0 0x1000>,
0x0 0x30000000 0x0 0x10000000>; <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <42>; interrupts = <42>;
clocks = <&prci FU740_PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
@ -237,8 +237,8 @@
compatible = "sifive,fu540-c000-gem"; compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <55>; interrupts = <55>;
reg = <0x0 0x10090000 0x0 0x2000 reg = <0x0 0x10090000 0x0 0x2000>,
0x0 0x100a0000 0x0 0x1000>; <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00]; local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk"; clock-names = "pclk", "hclk";
clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
@ -251,7 +251,7 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>; reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <44 45 46 47>; interrupts = <44>, <45>, <46>, <47>;
clocks = <&prci FU740_PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
@ -260,7 +260,7 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>; reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <48 49 50 51>; interrupts = <48>, <49>, <50>, <51>;
clocks = <&prci FU740_PRCI_CLK_PCLK>; clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
@ -273,7 +273,7 @@
cache-size = <2097152>; cache-size = <2097152>;
cache-unified; cache-unified;
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupts = <19 21 22 20>; interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>; reg = <0x0 0x2010000 0x0 0x1000>;
}; };
gpio: gpio@10060000 { gpio: gpio@10060000 {
@ -291,24 +291,23 @@
status = "disabled"; status = "disabled";
}; };
pcie@e00000000 { pcie@e00000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#num-lanes = <8>;
#size-cells = <2>;
compatible = "sifive,fu740-pcie"; compatible = "sifive,fu740-pcie";
reg = <0xe 0x00000000 0x1 0x0 #address-cells = <3>;
0xd 0xf0000000 0x0 0x10000000 #size-cells = <2>;
0x0 0x100d0000 0x0 0x1000>; #interrupt-cells = <1>;
reg = <0xe 0x00000000 0x0 0x80000000>,
<0xd 0xf0000000 0x0 0x10000000>,
<0x0 0x100d0000 0x0 0x1000>;
reg-names = "dbi", "config", "mgmt"; reg-names = "dbi", "config", "mgmt";
device_type = "pci"; device_type = "pci";
dma-coherent; dma-coherent;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
num-lanes = <0x8>; num-lanes = <0x8>;
interrupts = <56 57 58 59 60 61 62 63 64>; interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
interrupt-names = "msi", "inta", "intb", "intc", "intd"; interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic0>; interrupt-parent = <&plic0>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -316,13 +315,11 @@
<0x0 0x0 0x0 0x2 &plic0 58>, <0x0 0x0 0x0 0x2 &plic0 58>,
<0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x3 &plic0 59>,
<0x0 0x0 0x0 0x4 &plic0 60>; <0x0 0x0 0x0 0x4 &plic0 60>;
clock-names = "pcie_aux";
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
pwren-gpios = <&gpio 5 0>; pwren-gpios = <&gpio 5 0>;
reset-gpios = <&gpio 8 0>; reset-gpios = <&gpio 8 0>;
clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; resets = <&prci 4>;
clock-names = "pcie_aux";
resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
reset-names = "rst_n";
status = "okay"; status = "okay";
}; };
}; };

80
arch/riscv/dts/hifive-unmatched-a00.dts
View file

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2019-2021 SiFive, Inc */ /* Copyright (c) 2020 SiFive, Inc */
#include "fu740-c000.dtsi" #include "fu740-c000.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
@ -9,8 +9,6 @@
#define RTCCLK_FREQ 1000000 #define RTCCLK_FREQ 1000000
/ { / {
#address-cells = <2>;
#size-cells = <2>;
model = "SiFive HiFive Unmatched A00"; model = "SiFive HiFive Unmatched A00";
compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
"sifive,fu740"; "sifive,fu740";
@ -28,9 +26,6 @@
reg = <0x0 0x80000000 0x4 0x00000000>; reg = <0x0 0x80000000 0x4 0x00000000>;
}; };
soc {
};
hfclk: hfclk { hfclk: hfclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -65,10 +60,21 @@
temperature-sensor@4c { temperature-sensor@4c {
compatible = "ti,tmp451"; compatible = "ti,tmp451";
reg = <0x4c>; reg = <0x4c>;
vcc-supply = <&vdd_bpro>;
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>; interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
}; };
eeprom@54 {
compatible = "microchip,24c02", "atmel,24c02";
reg = <0x54>;
vcc-supply = <&vdd_bpro>;
label = "board-id";
pagesize = <16>;
read-only;
size = <256>;
};
pmic@58 { pmic@58 {
compatible = "dlg,da9063"; compatible = "dlg,da9063";
reg = <0x58>; reg = <0x58>;
@ -89,47 +95,31 @@
}; };
regulators { regulators {
vdd_bcore1: bcore1 { vdd_bcore: bcores-merged {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>; regulator-min-microamp = <4800000>;
regulator-max-microamp = <5000000>; regulator-max-microamp = <4800000>;
regulator-always-on;
};
vdd_bcore2: bcore2 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-min-microamp = <5000000>;
regulator-max-microamp = <5000000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bpro: bpro { vdd_bpro: bpro {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <2500000>; regulator-min-microamp = <2400000>;
regulator-max-microamp = <2500000>; regulator-max-microamp = <2400000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bperi: bperi { vdd_bperi: bperi {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1060000>;
regulator-min-microamp = <1500000>; regulator-min-microamp = <1500000>;
regulator-max-microamp = <1500000>; regulator-max-microamp = <1500000>;
regulator-always-on; regulator-always-on;
}; };
vdd_bmem: bmem { vdd_bmem_bio: bmem-bio-merged {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3000000>;
regulator-max-microamp = <3000000>;
regulator-always-on;
};
vdd_bio: bio {
regulator-min-microvolt = <1200000>; regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>; regulator-max-microvolt = <1200000>;
regulator-min-microamp = <3000000>; regulator-min-microamp = <3000000>;
@ -140,86 +130,66 @@
vdd_ldo1: ldo1 { vdd_ldo1: ldo1 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <100000>;
regulator-max-microamp = <100000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo2: ldo2 { vdd_ldo2: ldo2 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo3: ldo3 { vdd_ldo3: ldo3 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo4: ldo4 { vdd_ldo4: ldo4 {
regulator-min-microvolt = <2500000>; regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>; regulator-max-microvolt = <2500000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo5: ldo5 { vdd_ldo5: ldo5 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <100000>;
regulator-max-microamp = <100000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo6: ldo6 { vdd_ldo6: ldo6 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo7: ldo7 { vdd_ldo7: ldo7 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ldo8: ldo8 { vdd_ldo8: ldo8 {
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microamp = <200000>;
regulator-max-microamp = <200000>;
regulator-always-on; regulator-always-on;
}; };
vdd_ld09: ldo9 { vdd_ld09: ldo9 {
regulator-min-microvolt = <1050000>; regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>; regulator-max-microvolt = <1050000>;
regulator-min-microamp = <200000>; regulator-always-on;
regulator-max-microamp = <200000>;
}; };
vdd_ldo10: ldo10 { vdd_ldo10: ldo10 {
regulator-min-microvolt = <1000000>; regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>; regulator-max-microvolt = <1000000>;
regulator-min-microamp = <300000>; regulator-always-on;
regulator-max-microamp = <300000>;
}; };
vdd_ldo11: ldo11 { vdd_ldo11: ldo11 {
regulator-min-microvolt = <2500000>; regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>; regulator-max-microvolt = <2500000>;
regulator-min-microamp = <300000>;
regulator-max-microamp = <300000>;
regulator-always-on; regulator-always-on;
}; };
}; };
@ -269,4 +239,8 @@
&gpio { &gpio {
status = "okay"; status = "okay";
gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3",
"PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN",
"ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4",
"EN_VDD_SD", "SD_CD";
}; };