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clk: Ensure the parent clocks are enabled while reparenting

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Reparenting a clock C with a new parent P means that C will only
continue clocking if P is already clocking when the mux is updated. In
case the parent is currently disabled, failures (stalls) are likely to
happen.

This is exactly what happens on i.MX8 when enabling the video
pipeline. We tell LCDIF clocks to use the VIDEO PLL as input, while the
VIDEO PLL is currently off. This all happens as part of the
assigned-clocks handling procedure, where the reparenting happens before
the enable() calls. Enabling the parents as part of the reparenting
procedure seems sane and also matches the logic applied in other parts
of the CCM.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Miquel Raynal 2025-04-03 09:39:06 +02:00 • committed by Fabio Estevam
parent 197376fbf3
commit ac30d90f33
1 changed files with 17 additions and 4 deletions
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19
drivers/clk/clk-uclass.c
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@ -623,15 +623,28 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
if (!ops->set_parent)
return -ENOSYS;
ret = clk_enable(parent);
if (ret) {
printf("Cannot enable parent %s\n", parent->dev->name);
return ret;
}
ret = ops->set_parent(clk, parent);
if (ret)
if (ret) {
clk_disable(parent);
return ret;
}
if (CONFIG_IS_ENABLED(CLK_CCF))
if (CONFIG_IS_ENABLED(CLK_CCF)) {
ret = device_reparent(clk->dev, parent->dev);
if (ret) {
clk_disable(parent);
return ret;
}
}
return 0;
}
int clk_enable(struct clk *clk)
{