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net: dwc_eth_qos: Allow platform to override tx/rx_fifo_sz

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The GMAC controller on QCS404 SoC (support added by upcoming patch) fails
to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So
allow platforms to override FIFO size using corresponding DT node
properties.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Sumit Garg 2023-02-01 19:28:54 +05:30 • committed by Tom Rini
parent 9d53f335f6
commit a962b7cff4
2 changed files with 14 additions and 6 deletions
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19
drivers/net/dwc_eth_qos.c
View file

@ -852,12 +852,19 @@ static int eqos_start(struct udevice *dev)
rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
/*
* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
* r/tqs is encoded as (n / 256) - 1.
*/
tqs = (128 << tx_fifo_sz) / 256 - 1;
rqs = (128 << rx_fifo_sz) / 256 - 1;
/* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */
tx_fifo_sz = 128 << tx_fifo_sz;
rx_fifo_sz = 128 << rx_fifo_sz;
/* Allow platform to override TX/RX fifo size */
if (eqos->tx_fifo_sz)
tx_fifo_sz = eqos->tx_fifo_sz;
if (eqos->rx_fifo_sz)
rx_fifo_sz = eqos->rx_fifo_sz;
/* r/tqs is encoded as (n / 256) - 1 */
tqs = tx_fifo_sz / 256 - 1;
rqs = rx_fifo_sz / 256 - 1;
clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<

1
drivers/net/dwc_eth_qos.h
View file

@ -276,6 +276,7 @@ struct eqos_priv {
bool started;
bool reg_access_ok;
bool clk_ck_enabled;
unsigned int tx_fifo_sz, rx_fifo_sz;
};
void eqos_inval_desc_generic(void *desc);