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fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

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DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu 2015-11-20 15:52:04 +08:00 • committed by York Sun
parent a07bdad749
commit a46b1852de
3 changed files with 39 additions and 3 deletions
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2
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -807,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define MAX_QE_RISC 1 #define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28 #define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
@ -854,6 +855,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define MAX_QE_RISC 1 #define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28 #define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500 #define CONFIG_E6500

9
drivers/ddr/fsl/fsl_ddr_gen4.c
View file

@ -10,6 +10,7 @@
#include <asm/processor.h> #include <asm/processor.h>
#include <fsl_immap.h> #include <fsl_immap.h>
#include <fsl_ddr.h> #include <fsl_ddr.h>
#include <fsl_errata.h>
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
@ -238,9 +239,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
/* Erratum applies when accumulated ECC is used, or DBI is enabled */ /* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4) #define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || if (has_erratum_a008378()) {
IS_DBI(regs->ddr_sdram_cfg_3)) if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
ddr_setbits32(ddr->debug[28], 0x9 << 20); IS_DBI(regs->ddr_sdram_cfg_3))
ddr_setbits32(&ddr->debug[28], 0x9 << 20);
}
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511

31
include/fsl_errata.h
View file

@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void)
} }
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
static inline bool has_erratum_a008378(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_LS102XA
case SOC_VER_LS1020:
case SOC_VER_LS1021:
case SOC_VER_LS1022:
case SOC_VER_SLS1020:
return IS_SVR_REV(svr, 1, 0);
#endif
#ifdef CONFIG_PPC
case SVR_T1023:
case SVR_T1024:
return IS_SVR_REV(svr, 1, 0);
case SVR_T1020:
case SVR_T1022:
case SVR_T1040:
case SVR_T1042:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
default:
return false;
}
}
#endif
#endif /* _FSL_ERRATA_H */ #endif /* _FSL_ERRATA_H */