Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-08 10:39:08 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

Browse source 
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu 2015-11-20 15:52:04 +08:00 • committed by York Sun
parent a07bdad749
commit a46b1852de
3 changed files with 39 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

9
drivers/ddr/fsl/fsl_ddr_gen4.c
View file

@ -10,6 +10,7 @@
#include <asm/processor.h>
#include <fsl_immap.h>
#include <fsl_ddr.h>
#include <fsl_errata.h>
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
@ -238,9 +239,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
/* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
IS_DBI(regs->ddr_sdram_cfg_3))
ddr_setbits32(ddr->debug[28], 0x9 << 20);
if (has_erratum_a008378()) {
if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
IS_DBI(regs->ddr_sdram_cfg_3))
ddr_setbits32(&ddr->debug[28], 0x9 << 20);
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008511