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sunxi: sun4i: make more clock functions SPL only

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In clock_sun4i.c, responsible for (mostly early) clock setup on early
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.

Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.

This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.

This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-12-07 16:06:51 +00:00
parent 8cb3c49454
commit a2b2a47a16
1 changed files with 2 additions and 3 deletions
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5
arch/arm/mach-sunxi/clock_sun4i.c
View file

@ -43,7 +43,6 @@ void clock_init_safe(void)
setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
#endif #endif
} }
#endif
void clock_init_uart(void) void clock_init_uart(void)
{ {
@ -77,7 +76,6 @@ int clock_twi_onoff(int port, int state)
return 0; return 0;
} }
#ifdef CONFIG_SPL_BUILD
#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \ #define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \ 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \ 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
@ -177,8 +175,9 @@ void clock_set_pll1(unsigned int hz)
&ccm->cpu_ahb_apb0_cfg); &ccm->cpu_ahb_apb0_cfg);
sdelay(20); sdelay(20);
} }
#endif #endif /* CONFIG_SPL_BUILD */
/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk) void clock_set_pll3(unsigned int clk)
{ {
struct sunxi_ccm_reg * const ccm = struct sunxi_ccm_reg * const ccm =