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serial: pl01x: Modify pending callback to test if transmit FIFO is empty

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Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.

This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().

The fix here is to test explicitly if the TX FIFO is empty.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski 2023-05-19 12:43:53 +02:00 • committed by Stefano Babic
parent 875752adc8
commit a217891948
1 changed files with 1 additions and 1 deletions
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2
drivers/serial/serial_pl01x.c
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@ -329,7 +329,7 @@ int pl01x_serial_pending(struct udevice *dev, bool input)
if (input)
return pl01x_tstc(priv->regs);
else
return fr & UART_PL01x_FR_TXFF ? 0 : 1;
return fr & UART_PL01x_FR_TXFE ? 0 : 1;
}
static const struct dm_serial_ops pl01x_serial_ops = {