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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

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This commit is contained in:
Tom Rini 2025-01-29 19:06:55 -06:00
commit 9f5d1863e9
44 changed files with 125 additions and 405 deletions
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2
board/beacon/beacon-rzg2m/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := beacon-rzg2m.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
obj-y := beacon-rzg2m.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o

2
board/hoperun/hihope-rzg2/Makefile
View file

@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := hihope-rzg2.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
obj-y := hihope-rzg2.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o

49
board/renesas/common/Makefile Normal file
View file

@ -0,0 +1,49 @@
#
# board/renesas/whitehawk/Makefile
#
# Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
# R-Car SoCs
ifndef CONFIG_RZG2L
# 32 bit SoCs
ifdef CONFIG_RCAR_32
ifdef CONFIG_RCAR_GEN2
endif
endif
# 64 bit SoCs
ifdef CONFIG_RCAR_64
ifdef CONFIG_XPL_BUILD
obj-y += rcar64-spl.o
else
obj-y += rcar64-common.o
endif
ifdef CONFIG_RCAR_GEN3
ifdef CONFIG_XPL_BUILD
obj-y += gen3-spl.o
else
obj-y += gen3-common.o
ifdef CONFIG_R8A77970
obj-y += v3-common.o
endif
ifdef CONFIG_R8A77980
obj-y += v3-common.o
endif
endif
endif
ifdef CONFIG_RCAR_GEN4
ifdef CONFIG_XPL_BUILD
obj-y += gen4-spl.o
else
obj-y += gen4-common.o
endif
endif
endif
endif

5
board/renesas/rcar-common/gen3-common.c → board/renesas/common/gen3-common.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* board/renesas/rcar-common/gen3-common.c
* board/renesas/common/gen3-common.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
@ -18,8 +18,6 @@
#include <asm/arch/renesas.h>
#include <linux/libfdt.h>
#ifdef CONFIG_RCAR_64
DECLARE_GLOBAL_DATA_PTR;
/* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */
@ -178,4 +176,3 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
#endif
#endif

38
board/renesas/common/gen3-spl.c Normal file
View file

@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Gen3 recovery SPL
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <init.h>
#include <asm/io.h>
#include <spl.h>
#define RCAR_CNTC_BASE 0xE6080000
#define CNTCR_EN BIT(0)
void board_init_f(ulong dummy)
{
writel(CNTCR_EN, RCAR_CNTC_BASE);
timer_init();
}
void spl_board_init(void)
{
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_UART;
}
void s_init(void)
{
}
void reset_cpu(void)
{
}

2
board/renesas/rcar-common/gen4-common.c → board/renesas/common/gen4-common.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board/renesas/rcar-common/gen4-common.c
* board/renesas/common/gen4-common.c
*
* Copyright (C) 2021-2024 Renesas Electronics Corp.
*/

17
board/renesas/rcar-common/gen4-spl.c → board/renesas/common/gen4-spl.c
View file

@ -76,23 +76,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
debug("image entry point: 0x%lx\n", spl_image->entry_point);
if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
typedef void (*image_entry_arg_t)(int, int, int, int)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t)(uintptr_t) spl_image->entry_point;
image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
} else {
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
(image_entry_noargs_t)spl_image->entry_point;
image_entry();
}
}
#define APMU_BASE 0xe6170000U
#define CL0GRP3_BIT BIT(3)
#define CL1GRP3_BIT BIT(7)

9
board/renesas/rcar-common/common.c → board/renesas/common/rcar64-common.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* board/renesas/rcar-common/common.c
* board/renesas/common/common.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
@ -18,8 +18,6 @@
#include <asm/system.h>
#include <linux/libfdt.h>
#ifdef CONFIG_RCAR_64
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
@ -68,4 +66,7 @@ int __weak board_init(void)
return 0;
}
#endif
int __weak board_early_init_f(void)
{
return 0;
}

39
board/renesas/rcar-common/gen3-spl.c → board/renesas/common/rcar64-spl.c
View file

@ -1,37 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-License-Identifier: GPL-2.0+
/*
* R-Car Gen3 recovery SPL
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
*/
#include <cpu_func.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/io.h>
#include <spl.h>
#include <linux/bitops.h>
#define RCAR_CNTC_BASE 0xE6080000
#define CNTCR_EN BIT(0)
void board_init_f(ulong dummy)
{
writel(CNTCR_EN, RCAR_CNTC_BASE);
timer_init();
}
void spl_board_init(void)
{
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_UART;
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
@ -49,11 +22,3 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
image_entry();
}
}
void s_init(void)
{
}
void reset_cpu(void)
{
}

0
board/renesas/rcar-common/v3-common.c → board/renesas/common/v3-common.c
View file

13
board/renesas/condor/Makefile
View file

@ -1,13 +0,0 @@
#
# board/renesas/condor/Makefile
#
# Copyright (C) 2019 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o
endif

6
board/renesas/draak/Makefile
View file

@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := draak.o ../rcar-common/gen3-common.o ../rcar-common/common.o
ifndef CONFIG_XPL_BUILD
obj-y += draak.o
endif

33
board/renesas/draak/draak.c
View file

@ -6,43 +6,12 @@
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*/
#include <cpu_func.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/renesas.h>
DECLARE_GLOBAL_DATA_PTR;
#define GSX_MSTP112 BIT(12) /* 3DG */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)

13
board/renesas/eagle/Makefile
View file

@ -1,13 +0,0 @@
#
# board/renesas/eagle/Makefile
#
# Copyright (C) 2015 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
endif

13
board/renesas/ebisu/Makefile
View file

@ -1,13 +0,0 @@
#
# board/renesas/ebisu/Makefile
#
# Copyright (C) 2018 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o
endif

13
board/renesas/falcon/Makefile
View file

@ -1,13 +0,0 @@
#
# board/renesas/falcon/Makefile
#
# Copyright (C) 2020 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o
endif

9
board/renesas/grayhawk/Makefile
View file

@ -1,9 +0,0 @@
#
# board/renesas/grayhawk/Makefile
#
# Copyright (C) 2023 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o

6
board/renesas/salvator-x/Makefile
View file

@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := salvator-x.o ../rcar-common/gen3-common.o ../rcar-common/common.o
ifndef CONFIG_XPL_BUILD
obj-y += salvator-x.o
endif

39
board/renesas/salvator-x/salvator-x.c
View file

@ -7,41 +7,13 @@
* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#include <cpu_func.h>
#include <image.h>
#include <init.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/renesas.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
@ -65,13 +37,6 @@ int board_init(void)
return 0;
}
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
void reset_cpu(void)
{
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
}
#endif
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
{

9
board/renesas/spider/Makefile
View file

@ -1,9 +0,0 @@
#
# board/renesas/spider/Makefile
#
# Copyright (C) 2020 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o

6
board/renesas/ulcb/Makefile
View file

@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ulcb.o cpld.o ../rcar-common/gen3-common.o ../rcar-common/common.o
ifndef CONFIG_XPL_BUILD
obj-y += ulcb.o cpld.o
endif

31
board/renesas/ulcb/ulcb.c
View file

@ -6,40 +6,13 @@
* Copyright (C) 2017 Renesas Electronics Corporation
*/
#include <image.h>
#include <init.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <i2c.h>
#include <mmc.h>
#include <asm/arch/renesas.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)

5
board/renesas/v3hsk/Makefile
View file

@ -7,9 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SYSRESET) += cpld.o
endif

5
board/renesas/v3msk/Makefile
View file

@ -7,9 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_XPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SYSRESET) += cpld.o
endif

13
board/renesas/whitehawk/Makefile
View file

@ -1,13 +0,0 @@
#
# board/renesas/whitehawk/Makefile
#
# Copyright (C) 2021 Renesas Electronics Corp.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen4-spl.o
else
obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o
endif

4
board/silinux/ek874/Makefile
View file

@ -7,7 +7,7 @@
#
ifdef CONFIG_XPL_BUILD
obj-y := ../../renesas/rcar-common/gen3-spl.o
obj-y := ../../renesas/common/gen3-spl.o
else
obj-y := ek874.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o
obj-y := ek874.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o
endif

1
configs/alt_defconfig
View file

@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/controlcenterdc_defconfig
View file

@ -85,7 +85,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ANEG_TIMEOUT=8000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y

1
configs/gose_defconfig
View file

@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/grpeach_defconfig
View file

@ -52,7 +52,6 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH_PHY=y
CONFIG_SH_ETHER=y

1
configs/koelsch_defconfig
View file

@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/lager_defconfig
View file

@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/porter_defconfig
View file

@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/r8a779a0_falcon_defconfig
View file

@ -17,7 +17,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb"
CONFIG_SYS_PBSIZE=2068
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y

1
configs/r8a779g0_whitehawk_defconfig
View file

@ -19,7 +19,6 @@ CONFIG_SYS_CBSIZE=2048
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y

1
configs/r8a779h0_grayhawk_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_SYS_CBSIZE=2048
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_RENESAS_RAVB=y

1
configs/renesas_rcar3.config
View file

@ -1,5 +1,4 @@
#include <configs/renesas_rcar64.config>
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_SYS_PBSIZE=2068

1
configs/silk_defconfig
View file

@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

1
configs/stout_defconfig
View file

@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k
CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_BITBANGMII=y
CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_SH_ETHER=y

25
doc/README.bitbangMII
View file

@ -7,28 +7,11 @@ The driver requires that the following macros should be defined into the board
configuration file:
CONFIG_BITBANGMII - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support
If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:
MII_INIT - Generic code to enable the MII bus (optional)
MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ - Read the MDIO pin
MDIO(v) - Write v on the MDIO pin
MDC_DECLARE - Declaration needed to access to the MDC pin (optional)
MDC(v) - Write v on the MDC pin
The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).
When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):
The board code needs to fill the bb_miiphy_buses[] array with a record for
each required bus and declare the bb_miiphy_buses_num variable with the
number of mii buses. The record (struct bb_miiphy_bus) has the following
fields/callbacks (see miiphy.h for details):
char name[] - The symbolic name that must be equal to the MII bus
registered name

4
drivers/net/phy/Kconfig
View file

@ -2,10 +2,6 @@
config BITBANGMII
bool "Bit-banged ethernet MII management channel support"
config BITBANGMII_MULTI
bool "Enable the multi bus support"
depends on BITBANGMII
config MV88E6352_SWITCH
bool "Marvell 88E6352 switch support"

89
drivers/net/phy/miiphybb.c
View file

@ -17,90 +17,6 @@
#include <miiphy.h>
#include <asm/global_data.h>
#ifndef CONFIG_BITBANGMII_MULTI
/*
* If CONFIG_BITBANGMII_MULTI is not defined we use a
* compatibility layer with the previous miiphybb implementation
* based on macros usage.
*
*/
static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MII_INIT
MII_INIT;
#endif
return 0;
}
static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO_ACTIVE;
return 0;
}
static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO_TRISTATE;
return 0;
}
static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO(v);
return 0;
}
static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
*v = MDIO_READ;
return 0;
}
static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
{
#ifdef MDC_DECLARE
MDC_DECLARE;
#endif
MDC(v);
return 0;
}
static int bb_delay_wrap(struct bb_miiphy_bus *bus)
{
MIIDELAY;
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = BB_MII_DEVNAME,
.init = bb_mii_init_wrap,
.mdio_active = bb_mdio_active_wrap,
.mdio_tristate = bb_mdio_tristate_wrap,
.set_mdio = bb_set_mdio_wrap,
.get_mdio = bb_get_mdio_wrap,
.set_mdc = bb_set_mdc_wrap,
.delay = bb_delay_wrap,
}
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
#endif
int bb_miiphy_init(void)
{
int i;
@ -114,7 +30,6 @@ int bb_miiphy_init(void)
static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
{
#ifdef CONFIG_BITBANGMII_MULTI
int i;
/* Search the correct bus */
@ -124,10 +39,6 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
}
}
return NULL;
#else
/* We have just one bitbanging bus */
return &bb_miiphy_buses[0];
#endif
}
/*****************************************************************************

14
drivers/net/ravb.c
View file

@ -560,12 +560,12 @@ static int ravb_remove(struct udevice *dev)
return 0;
}
int ravb_bb_init(struct bb_miiphy_bus *bus)
static int ravb_bb_init(struct bb_miiphy_bus *bus)
{
return 0;
}
int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
@ -574,7 +574,7 @@ int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
return 0;
}
int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct ravb_priv *eth = bus->priv;
@ -583,7 +583,7 @@ int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
return 0;
}
int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
@ -595,7 +595,7 @@ int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
return 0;
}
int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct ravb_priv *eth = bus->priv;
@ -604,7 +604,7 @@ int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
return 0;
}
int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct ravb_priv *eth = bus->priv;
@ -616,7 +616,7 @@ int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
return 0;
}
int ravb_bb_delay(struct bb_miiphy_bus *bus)
static int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(10);

4
include/miiphy.h
View file

@ -64,7 +64,7 @@ void mdio_list_devices(void);
#define BB_MII_DEVNAME "bb_miiphy"
struct bb_miiphy_bus {
char name[16];
char name[MDIO_NAME_LEN];
int (*init)(struct bb_miiphy_bus *bus);
int (*mdio_active)(struct bb_miiphy_bus *bus);
int (*mdio_tristate)(struct bb_miiphy_bus *bus);
@ -72,9 +72,7 @@ struct bb_miiphy_bus {
int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
int (*delay)(struct bb_miiphy_bus *bus);
#ifdef CONFIG_BITBANGMII_MULTI
void *priv;
#endif
};
extern struct bb_miiphy_bus bb_miiphy_buses[];