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video: imx: Add LCDIF driver
Add support for the LCD interfaces (LCDIF1/2). When probed, these interfaces request numerous clocks and power domains, attach the bridge and look for a panel in order to retrieve its capabilities and properties. There is a similar existing driver in the upper folder for other i.MX targets, I discovered this driver a bit late. It is not targeting the i.MX8MP and I have no idea how different can the LCDIF be on this SoC, but I did not manage to get it work, especially because it is not fully compliant with the device-model, especially on the clocks/power management side which is all ad-hoc. This is normal though, it was contributed more than ten years ago. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Miquel Raynal
parent
c45c028e76
commit
9eafbb6ac1
3 changed files with 318 additions and 0 deletions
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@ -19,3 +19,6 @@ config IMX_LDB
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depends on VIDEO_BRIDGE
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help
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Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
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config IMX_LCDIF
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bool "i.MX LCDIFv3 LCD controller"
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@ -5,3 +5,4 @@
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obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
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obj-$(CONFIG_IMX_LDB) += ldb.o
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obj-$(CONFIG_IMX_LCDIF) += lcdif.o
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314
drivers/video/imx/lcdif.c
Normal file
314
drivers/video/imx/lcdif.c
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@ -0,0 +1,314 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* i.MX8 LCD interface driver inspired from the Linux driver
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* Copyright 2019 NXP
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* Copyright 2024 Bootlin
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* Adapted by Miquel Raynal <miquel.raynal@bootlin.com>
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*/
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#include <asm/io.h>
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#include <asm/mach-imx/dma.h>
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#include <clk.h>
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#include <dm.h>
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#include <panel.h>
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#include <power-domain.h>
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#include <video.h>
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#include <video_bridge.h>
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#include <linux/delay.h>
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#include "../videomodes.h"
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#define LCDIFV3_CTRL 0x0
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#define LCDIFV3_CTRL_SET 0x4
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#define LCDIFV3_CTRL_CLR 0x8
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#define CTRL_INV_HS BIT(0)
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#define CTRL_INV_VS BIT(1)
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#define CTRL_INV_DE BIT(2)
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#define CTRL_INV_PXCK BIT(3)
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#define CTRL_CLK_GATE BIT(30)
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#define CTRL_SW_RESET BIT(31)
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#define LCDIFV3_DISP_PARA 0x10
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#define DISP_PARA_DISP_MODE_NORMAL 0
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#define DISP_PARA_LINE_PATTERN_RGB_YUV 0
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#define DISP_PARA_DISP_ON BIT(31)
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#define LCDIFV3_DISP_SIZE 0x14
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#define DISP_SIZE_DELTA_X(x) ((x) & 0xffff)
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#define DISP_SIZE_DELTA_Y(x) ((x) << 16)
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#define LCDIFV3_HSYN_PARA 0x18
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#define HSYN_PARA_FP_H(x) ((x) & 0xffff)
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#define HSYN_PARA_BP_H(x) ((x) << 16)
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#define LCDIFV3_VSYN_PARA 0x1C
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#define VSYN_PARA_FP_V(x) ((x) & 0xffff)
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#define VSYN_PARA_BP_V(x) ((x) << 16)
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#define LCDIFV3_VSYN_HSYN_WIDTH 0x20
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#define VSYN_HSYN_PW_H(x) ((x) & 0xffff)
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#define VSYN_HSYN_PW_V(x) ((x) << 16)
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#define LCDIFV3_CTRLDESCL0_1 0x200
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#define CTRLDESCL0_1_WIDTH(x) ((x) & 0xffff)
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#define CTRLDESCL0_1_HEIGHT(x) ((x) << 16)
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#define LCDIFV3_CTRLDESCL0_3 0x208
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#define CTRLDESCL0_3_PITCH(x) ((x) & 0xFFFF)
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#define LCDIFV3_CTRLDESCL_LOW0_4 0x20C
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#define LCDIFV3_CTRLDESCL_HIGH0_4 0x210
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#define LCDIFV3_CTRLDESCL0_5 0x214
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#define CTRLDESCL0_5_YUV_FORMAT(x) (((x) & 0x3) << 14)
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#define CTRLDESCL0_5_BPP(x) (((x) & 0xf) << 24)
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#define BPP32_ARGB8888 0x9
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#define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30)
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#define CTRLDESCL0_5_EN BIT(31)
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struct lcdifv3_priv {
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void __iomem *base;
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struct clk pix_clk;
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struct power_domain pd;
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struct udevice *panel;
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struct udevice *bridge;
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};
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static void lcdifv3_set_mode(struct lcdifv3_priv *priv,
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struct display_timing *timings)
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{
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u32 reg;
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writel(DISP_SIZE_DELTA_X(timings->hactive.typ) |
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DISP_SIZE_DELTA_Y(timings->vactive.typ),
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priv->base + LCDIFV3_DISP_SIZE);
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writel(HSYN_PARA_FP_H(timings->hfront_porch.typ) |
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HSYN_PARA_BP_H(timings->hback_porch.typ),
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priv->base + LCDIFV3_HSYN_PARA);
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writel(VSYN_PARA_BP_V(timings->vback_porch.typ) |
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VSYN_PARA_FP_V(timings->vfront_porch.typ),
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priv->base + LCDIFV3_VSYN_PARA);
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writel(VSYN_HSYN_PW_H(timings->hsync_len.typ) |
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VSYN_HSYN_PW_V(timings->vsync_len.typ),
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priv->base + LCDIFV3_VSYN_HSYN_WIDTH);
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writel(CTRLDESCL0_1_WIDTH(timings->hactive.typ) |
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CTRLDESCL0_1_HEIGHT(timings->vactive.typ),
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priv->base + LCDIFV3_CTRLDESCL0_1);
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if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
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writel(CTRL_INV_HS, priv->base + LCDIFV3_CTRL_SET);
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else
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writel(CTRL_INV_HS, priv->base + LCDIFV3_CTRL_CLR);
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if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
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writel(CTRL_INV_VS, priv->base + LCDIFV3_CTRL_SET);
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else
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writel(CTRL_INV_VS, priv->base + LCDIFV3_CTRL_CLR);
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if (timings->flags & DISPLAY_FLAGS_DE_LOW)
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writel(CTRL_INV_DE, priv->base + LCDIFV3_CTRL_SET);
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else
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writel(CTRL_INV_DE, priv->base + LCDIFV3_CTRL_CLR);
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if (timings->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
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writel(CTRL_INV_PXCK, priv->base + LCDIFV3_CTRL_SET);
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else
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writel(CTRL_INV_PXCK, priv->base + LCDIFV3_CTRL_CLR);
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writel(0, priv->base + LCDIFV3_DISP_PARA);
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reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
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reg &= ~(CTRLDESCL0_5_BPP(0xf) | CTRLDESCL0_5_YUV_FORMAT(0x3));
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reg |= CTRLDESCL0_5_BPP(BPP32_ARGB8888);
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writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
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}
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static void lcdifv3_enable_controller(struct lcdifv3_priv *priv)
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{
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u32 reg;
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reg = readl(priv->base + LCDIFV3_DISP_PARA);
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reg |= DISP_PARA_DISP_ON;
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writel(reg, priv->base + LCDIFV3_DISP_PARA);
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reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
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reg |= CTRLDESCL0_5_EN;
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writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
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}
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static int lcdifv3_video_sync(struct udevice *dev)
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{
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struct lcdifv3_priv *priv = dev_get_priv(dev);
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u32 reg;
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reg = readl(priv->base + LCDIFV3_CTRLDESCL0_5);
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reg |= CTRLDESCL0_5_SHADOW_LOAD_EN;
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writel(reg, priv->base + LCDIFV3_CTRLDESCL0_5);
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return 0;
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}
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static void lcdifv3_init(struct udevice *dev, struct display_timing *timings)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct lcdifv3_priv *priv = dev_get_priv(dev);
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clk_set_rate(&priv->pix_clk, timings->pixelclock.typ);
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writel(CTRL_SW_RESET | CTRL_CLK_GATE, priv->base + LCDIFV3_CTRL_CLR);
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udelay(10);
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lcdifv3_set_mode(priv, timings);
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writel(plat->base & 0xFFFFFFFF, priv->base + LCDIFV3_CTRLDESCL_LOW0_4);
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writel(plat->base >> 32, priv->base + LCDIFV3_CTRLDESCL_HIGH0_4);
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writel(CTRLDESCL0_3_PITCH(timings->hactive.typ * 4), /* 32bpp */
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priv->base + LCDIFV3_CTRLDESCL0_3);
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lcdifv3_enable_controller(priv);
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}
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static int lcdifv3_video_probe(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct lcdifv3_priv *priv = dev_get_priv(dev);
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struct clk axi_clk, disp_axi_clk;
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struct display_timing timings;
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u32 fb_start, fb_end;
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int ret;
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ret = power_domain_get(dev, &priv->pd);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "pix", &priv->pix_clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "axi", &axi_clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "disp_axi", &disp_axi_clk);
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if (ret < 0)
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return ret;
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ret = power_domain_on(&priv->pd);
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if (ret)
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return ret;
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ret = clk_enable(&priv->pix_clk);
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if (ret)
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goto dis_pd;
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ret = clk_enable(&axi_clk);
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if (ret)
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goto dis_pix_clk;
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ret = clk_enable(&disp_axi_clk);
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if (ret)
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goto dis_axi_clk;
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priv->base = dev_remap_addr(dev);
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if (!priv->base) {
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ret = -EINVAL;
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goto dis_clks;
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}
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/* Attach bridge */
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ret = uclass_get_device_by_endpoint(UCLASS_VIDEO_BRIDGE, dev,
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-1, -1, &priv->bridge);
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if (ret)
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goto dis_clks;
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ret = video_bridge_attach(priv->bridge);
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if (ret)
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goto dis_clks;
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ret = video_bridge_set_backlight(priv->bridge, 80);
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if (ret)
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goto dis_clks;
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/* Attach panels */
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ret = uclass_get_device_by_endpoint(UCLASS_PANEL, priv->bridge,
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1, -1, &priv->panel);
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if (ret) {
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ret = uclass_get_device_by_endpoint(UCLASS_PANEL, priv->bridge,
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2, -1, &priv->panel);
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if (ret)
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goto dis_clks;
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}
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ret = panel_get_display_timing(priv->panel, &timings);
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if (ret) {
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ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
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0, &timings);
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if (ret) {
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printf("Cannot decode panel timings (%d)\n", ret);
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goto dis_clks;
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}
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}
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lcdifv3_init(dev, &timings);
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/* Only support 32bpp for now */
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uc_priv->bpix = VIDEO_BPP32;
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uc_priv->xsize = timings.hactive.typ;
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uc_priv->ysize = timings.vactive.typ;
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/* Enable dcache for the frame buffer */
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fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
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fb_end = ALIGN(plat->base + plat->size, 1 << MMU_SECTION_SHIFT);
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mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
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DCACHE_WRITEBACK);
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video_set_flush_dcache(dev, true);
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return 0;
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dis_clks:
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clk_disable(&disp_axi_clk);
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dis_axi_clk:
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clk_disable(&axi_clk);
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dis_pix_clk:
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clk_disable(&priv->pix_clk);
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dis_pd:
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power_domain_off(&priv->pd);
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return ret;
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}
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static int lcdifv3_video_bind(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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/* Max size supported by LCDIF */
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plat->size = 1920 * 1080 * VNBYTES(VIDEO_BPP32);
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return 0;
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}
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static const struct udevice_id lcdifv3_video_ids[] = {
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{ .compatible = "fsl,imx8mp-lcdif" },
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{ }
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};
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static struct video_ops lcdifv3_video_ops = {
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.video_sync = lcdifv3_video_sync,
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};
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U_BOOT_DRIVER(lcdifv3_video) = {
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.name = "lcdif",
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.id = UCLASS_VIDEO,
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.of_match = lcdifv3_video_ids,
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.bind = lcdifv3_video_bind,
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.ops = &lcdifv3_video_ops,
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.probe = lcdifv3_video_probe,
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.priv_auto = sizeof(struct lcdifv3_priv),
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.flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
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};
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