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Merge tag 'u-boot-imx-next-20241209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

Browse source 
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/23736

- Add support for the NXP i.MX91 EVK board.
- Improve EEPRON suport on i.MX8MP DHCOM board.
- Switch phycore_imx8mm to using environment text files and improve
  environment handling.
This commit is contained in:
Tom Rini 2024-12-09 08:46:57 -06:00
commit 9dd0a9ecaa
49 changed files with 12023 additions and 101 deletions
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2
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
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@ -9,6 +9,8 @@
aliases {
eeprom0 = &eeprom0;
eeprom1 = &eeprom1;
eeprom0wl = &eeprom0wl;
eeprom1wl = &eeprom1wl;
mmc0 = &usdhc2; /* MicroSD */
mmc1 = &usdhc3; /* eMMC */
mmc2 = &usdhc1; /* SDIO */

195
arch/arm/dts/imx91-11x11-evk-u-boot.dtsi Normal file
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@ -0,0 +1,195 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*/
#include "imx91-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c1 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c2 {
bootph-pre-ram;
bootph-some-ram;
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
bootph-pre-ram;
bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_lpi2c1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_lpi2c2 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
};
&fec {
compatible = "fsl,imx91-fec", "fsl,imx93-fec", "fsl,imx8mq-fec";
phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&ethphy1 {
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
/delete-property/ assigned-clock-parents;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};

92
arch/arm/dts/imx91-u-boot.dtsi Normal file
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@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
*/
/ {
binman: binman {
multiple-images;
};
};
&A55_0 {
clocks = <&clk IMX93_CLK_A55_SEL>;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_imem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_dmem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_imem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_dmem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x204A0000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
u-boot-container {
filename = "u-boot-container.bin";
mkimage {
args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
blob {
filename = "u-boot.bin";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
filename = "spl.bin";
offset = <0x0>;
align-size = <0x400>;
align = <0x400>;
};
uboot: blob-ext@2 {
filename = "u-boot-container.bin";
};
};
};

5
arch/arm/include/asm/arch-imx/cpu.h
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@ -71,6 +71,11 @@
#define MXC_CPU_IMX9302 0xC9 /* dummy ID */
#define MXC_CPU_IMX9301 0xCA /* dummy ID */
#define MXC_CPU_IMX91 0xCB /* dummy ID */
#define MXC_CPU_IMX9121 0xCC /* dummy ID */
#define MXC_CPU_IMX9111 0xCD /* dummy ID */
#define MXC_CPU_IMX9101 0xCE /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_IMX8M 0x80

7
arch/arm/include/asm/arch-imx9/clock.h
View file

@ -205,10 +205,17 @@ struct clk_root_map {
u32 mux_type;
};
enum clk_soc {
CLK_SOC_ALL = 0,
CLK_SOC_IMX93 = 1,
CLK_SOC_IMX91 = 2,
};
struct imx_clk_setting {
u32 clk_root;
enum ccm_clk_src src;
u32 div;
enum clk_soc soc;
};
int clock_init_early(void);

2
arch/arm/include/asm/arch-imx9/gpio.h
View file

@ -6,6 +6,8 @@
#ifndef __ASM_ARCH_IMX9_GPIO_H
#define __ASM_ARCH_IMX9_GPIO_H
#include <linux/types.h>
struct gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;

770
arch/arm/include/asm/arch-imx9/imx91_pins.h Normal file
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@ -0,0 +1,770 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2024 NXP
*/
#ifndef __ASM_ARCH_IMX91_PINS_H__
#define __ASM_ARCH_IMX91_PINS_H__
#include <asm/mach-imx/iomux-v3.h>
enum {
MX91_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x01B0, 0x0000, 0x00, 0x03D8, 0x00, 0x00),
MX91_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x01B0, 0x0000, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x01B0, 0x0000, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x01B0, 0x0000, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x01B0, 0x0000, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x01B0, 0x0000, 0x06, 0x0488, 0x00, 0x00),
MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x01B4, 0x0004, 0x00, 0x03DC, 0x00, 0x00),
MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x01B4, 0x0004, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x01B4, 0x0004, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x01B4, 0x0004, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x01B8, 0x0008, 0x00, 0x03D4, 0x00, 0x00),
MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x01B8, 0x0008, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x01B8, 0x0008, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x01B8, 0x0008, 0x06, 0x0484, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x01BC, 0x000C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x01BC, 0x000C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x01BC, 0x000C, 0x03, 0x0364, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x01BC, 0x000C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x01BC, 0x000C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x01BC, 0x000C, 0x06, 0x048C, 0x00, 0x00),
MX91_PAD_GPIO_IO00__GPIO2_IO0 = IOMUX_PAD(0x01C0, 0x0010, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x01C0, 0x0010, 0x01, 0x03F4, 0x00, 0x00),
MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x01C0, 0x0010, 0x02, 0x04BC, 0x00, 0x00),
MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x01C0, 0x0010, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x01C0, 0x0010, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x01C0, 0x0010, 0x05, 0x048C, 0x01, 0x00),
MX91_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x01C0, 0x0010, 0x06, 0x0404, 0x00, 0x00),
MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 = IOMUX_PAD(0x01C0, 0x0010, 0x07, 0x036C, 0x00, 0x00),
MX91_PAD_GPIO_IO01__GPIO2_IO1 = IOMUX_PAD(0x01C4, 0x0014, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x01C4, 0x0014, 0x01, 0x03F0, 0x00, 0x00),
MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 = IOMUX_PAD(0x01C4, 0x0014, 0x02, 0x0490, 0x00, 0x00),
MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x01C4, 0x0014, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x01C4, 0x0014, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x01C4, 0x0014, 0x05, 0x0488, 0x01, 0x00),
MX91_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x01C4, 0x0014, 0x06, 0x0400, 0x00, 0x00),
MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 = IOMUX_PAD(0x01C4, 0x0014, 0x07, 0x0370, 0x00, 0x00),
MX91_PAD_GPIO_IO02__GPIO2_IO2 = IOMUX_PAD(0x01C8, 0x0018, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x01C8, 0x0018, 0x01, 0x03FC, 0x00, 0x00),
MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 0x02, 0x04C0, 0x00, 0x00),
MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x01C8, 0x0018, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x01C8, 0x0018, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x01C8, 0x0018, 0x05, 0x0484, 0x01, 0x00),
MX91_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x01C8, 0x0018, 0x06, 0x040C, 0x00, 0x00),
MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 = IOMUX_PAD(0x01C8, 0x0018, 0x07, 0x0374, 0x00, 0x00),
MX91_PAD_GPIO_IO03__GPIO2_IO3 = IOMUX_PAD(0x01CC, 0x001C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x01CC, 0x001C, 0x01, 0x03F8, 0x00, 0x00),
MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 0x02, 0x04B8, 0x00, 0x00),
MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x01CC, 0x001C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x01CC, 0x001C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x01CC, 0x001C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x01CC, 0x001C, 0x06, 0x0408, 0x00, 0x00),
MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 = IOMUX_PAD(0x01CC, 0x001C, 0x07, 0x0378, 0x00, 0x00),
MX91_PAD_GPIO_IO04__GPIO2_IO4 = IOMUX_PAD(0x01D0, 0x0020, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x01D0, 0x0020, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x01D0, 0x0020, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 = IOMUX_PAD(0x01D0, 0x0020, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x01D0, 0x0020, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x01D0, 0x0020, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x01D0, 0x0020, 0x06, 0x040C, 0x01, 0x00),
MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 = IOMUX_PAD(0x01D0, 0x0020, 0x07, 0x037C, 0x00, 0x00),
MX91_PAD_GPIO_IO05__GPIO2_IO5 = IOMUX_PAD(0x01D4, 0x0024, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x01D4, 0x0024, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 = IOMUX_PAD(0x01D4, 0x0024, 0x02, 0x04C4, 0x00, 0x00),
MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 = IOMUX_PAD(0x01D4, 0x0024, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x01D4, 0x0024, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x01D4, 0x0024, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x01D4, 0x0024, 0x06, 0x0408, 0x01, 0x00),
MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 = IOMUX_PAD(0x01D4, 0x0024, 0x07, 0x0380, 0x00, 0x00),
MX91_PAD_GPIO_IO06__GPIO2_IO6 = IOMUX_PAD(0x01D8, 0x0028, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x01D8, 0x0028, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 = IOMUX_PAD(0x01D8, 0x0028, 0x02, 0x04C8, 0x00, 0x00),
MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 = IOMUX_PAD(0x01D8, 0x0028, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x01D8, 0x0028, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x01D8, 0x0028, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x01D8, 0x0028, 0x06, 0x0414, 0x00, 0x00),
MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 = IOMUX_PAD(0x01D8, 0x0028, 0x07, 0x0384, 0x00, 0x00),
MX91_PAD_GPIO_IO07__GPIO2_IO7 = IOMUX_PAD(0x01DC, 0x002C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x01DC, 0x002C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 = IOMUX_PAD(0x01DC, 0x002C, 0x02, 0x0494, 0x00, 0x00),
MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 = IOMUX_PAD(0x01DC, 0x002C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x01DC, 0x002C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x01DC, 0x002C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x01DC, 0x002C, 0x06, 0x0410, 0x00, 0x00),
MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 = IOMUX_PAD(0x01DC, 0x002C, 0x07, 0x0388, 0x00, 0x00),
MX91_PAD_GPIO_IO08__GPIO2_IO8 = IOMUX_PAD(0x01E0, 0x0030, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x01E0, 0x0030, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 = IOMUX_PAD(0x01E0, 0x0030, 0x02, 0x0498, 0x00, 0x00),
MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 = IOMUX_PAD(0x01E0, 0x0030, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x01E0, 0x0030, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x01E0, 0x0030, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x01E0, 0x0030, 0x06, 0x0414, 0x01, 0x00),
MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 = IOMUX_PAD(0x01E0, 0x0030, 0x07, 0x038C, 0x00, 0x00),
MX91_PAD_GPIO_IO09__GPIO2_IO9 = IOMUX_PAD(0x01E4, 0x0034, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x01E4, 0x0034, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 = IOMUX_PAD(0x01E4, 0x0034, 0x02, 0x049C, 0x00, 0x00),
MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 = IOMUX_PAD(0x01E4, 0x0034, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x01E4, 0x0034, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x01E4, 0x0034, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x01E4, 0x0034, 0x06, 0x0410, 0x01, 0x00),
MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 = IOMUX_PAD(0x01E4, 0x0034, 0x07, 0x0390, 0x00, 0x00),
MX91_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x01E8, 0x0038, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x01E8, 0x0038, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 = IOMUX_PAD(0x01E8, 0x0038, 0x02, 0x04A0, 0x00, 0x00),
MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 = IOMUX_PAD(0x01E8, 0x0038, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x01E8, 0x0038, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x01E8, 0x0038, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x01E8, 0x0038, 0x06, 0x041C, 0x00, 0x00),
MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x01E8, 0x0038, 0x07, 0x0394, 0x00, 0x00),
MX91_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x01EC, 0x003C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x01EC, 0x003C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 = IOMUX_PAD(0x01EC, 0x003C, 0x02, 0x04A4, 0x00, 0x00),
MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 = IOMUX_PAD(0x01EC, 0x003C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x01EC, 0x003C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x01EC, 0x003C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x01EC, 0x003C, 0x06, 0x0418, 0x00, 0x00),
MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x01EC, 0x003C, 0x07, 0x0398, 0x00, 0x00),
MX91_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x01F0, 0x0040, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x01F0, 0x0040, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 = IOMUX_PAD(0x01F0, 0x0040, 0x02, 0x04CC, 0x00, 0x00),
MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 = IOMUX_PAD(0x01F0, 0x0040, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x01F0, 0x0040, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x01F0, 0x0040, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x01F0, 0x0040, 0x06, 0x041C, 0x01, 0x00),
MX91_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x01F0, 0x0040, 0x07, 0x04DC, 0x00, 0x00),
MX91_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x01F4, 0x0044, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x01F4, 0x0044, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 = IOMUX_PAD(0x01F4, 0x0044, 0x02, 0x04D0, 0x00, 0x00),
MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 = IOMUX_PAD(0x01F4, 0x0044, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x01F4, 0x0044, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x01F4, 0x0044, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x01F4, 0x0044, 0x06, 0x0418, 0x01, 0x00),
MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x01F4, 0x0044, 0x07, 0x039C, 0x00, 0x00),
MX91_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x01F8, 0x0048, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x01F8, 0x0048, 0x01, 0x0474, 0x00, 0x00),
MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 = IOMUX_PAD(0x01F8, 0x0048, 0x02, 0x04A8, 0x00, 0x00),
MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x01F8, 0x0048, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x01F8, 0x0048, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x01F8, 0x0048, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x01F8, 0x0048, 0x06, 0x0480, 0x00, 0x00),
MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x01F8, 0x0048, 0x07, 0x03A0, 0x00, 0x00),
MX91_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x01FC, 0x004C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x01FC, 0x004C, 0x01, 0x0470, 0x00, 0x00),
MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 = IOMUX_PAD(0x01FC, 0x004C, 0x02, 0x04AC, 0x00, 0x00),
MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x01FC, 0x004C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x01FC, 0x004C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x01FC, 0x004C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x01FC, 0x004C, 0x06, 0x047C, 0x00, 0x00),
MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x01FC, 0x004C, 0x07, 0x03A4, 0x00, 0x00),
MX91_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x0200, 0x0050, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x0200, 0x0050, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 = IOMUX_PAD(0x0200, 0x0050, 0x02, 0x04CC, 0x01, 0x00),
MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x0200, 0x0050, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x0200, 0x0050, 0x04, 0x046C, 0x00, 0x00),
MX91_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x0200, 0x0050, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x0200, 0x0050, 0x06, 0x0478, 0x00, 0x00),
MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x0200, 0x0050, 0x07, 0x03A8, 0x00, 0x00),
MX91_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x0204, 0x0054, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x0204, 0x0054, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 = IOMUX_PAD(0x0204, 0x0054, 0x02, 0x04B0, 0x00, 0x00),
MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x0204, 0x0054, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x0204, 0x0054, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x0204, 0x0054, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x0204, 0x0054, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x0204, 0x0054, 0x07, 0x03AC, 0x00, 0x00),
MX91_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x0208, 0x0058, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x0208, 0x0058, 0x01, 0x04D8, 0x00, 0x00),
MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 = IOMUX_PAD(0x0208, 0x0058, 0x02, 0x04B4, 0x00, 0x00),
MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x0208, 0x0058, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x0208, 0x0058, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x0208, 0x0058, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x0208, 0x0058, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x0208, 0x0058, 0x07, 0x03B0, 0x00, 0x00),
MX91_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x020C, 0x005C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x020C, 0x005C, 0x01, 0x04DC, 0x01, 0x00),
MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 = IOMUX_PAD(0x020C, 0x005C, 0x02, 0x04D0, 0x01, 0x00),
MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x020C, 0x005C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x020C, 0x005C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x020C, 0x005C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x020C, 0x005C, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 = IOMUX_PAD(0x020C, 0x005C, 0x07, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x0210, 0x0060, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 = IOMUX_PAD(0x0210, 0x0060, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 = IOMUX_PAD(0x0210, 0x0060, 0x02, 0x04C4, 0x01, 0x00),
MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x0210, 0x0060, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x0210, 0x0060, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x0210, 0x0060, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x0210, 0x0060, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x0210, 0x0060, 0x07, 0x03B4, 0x00, 0x00),
MX91_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x0214, 0x0064, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 = IOMUX_PAD(0x0214, 0x0064, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x0214, 0x0064, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x0214, 0x0064, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x0214, 0x0064, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x0214, 0x0064, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x0214, 0x0064, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x0214, 0x0064, 0x07, 0x04D8, 0x01, 0x00),
MX91_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x0218, 0x0068, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x0218, 0x0068, 0x01, 0x04E8, 0x00, 0x00),
MX91_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x0218, 0x0068, 0x02, 0x04E4, 0x00, 0x00),
MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x0218, 0x0068, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x0218, 0x0068, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x0218, 0x0068, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x0218, 0x0068, 0x06, 0x0404, 0x01, 0x00),
MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x0218, 0x0068, 0x07, 0x03B8, 0x00, 0x00),
MX91_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x021C, 0x006C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x021C, 0x006C, 0x01, 0x04EC, 0x00, 0x00),
MX91_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x021C, 0x006C, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x021C, 0x006C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x021C, 0x006C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x021C, 0x006C, 0x06, 0x0400, 0x01, 0x00),
MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x021C, 0x006C, 0x07, 0x03BC, 0x00, 0x00),
MX91_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x0220, 0x0070, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x0220, 0x0070, 0x01, 0x04F0, 0x00, 0x00),
MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x0220, 0x0070, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x0220, 0x0070, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x0220, 0x0070, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x0220, 0x0070, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x0220, 0x0070, 0x07, 0x03C0, 0x00, 0x00),
MX91_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x0224, 0x0074, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x0224, 0x0074, 0x01, 0x04F4, 0x00, 0x00),
MX91_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x0224, 0x0074, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x0224, 0x0074, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x0224, 0x0074, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x0224, 0x0074, 0x05, 0x03D4, 0x01, 0x00),
MX91_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x0224, 0x0074, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x0224, 0x0074, 0x07, 0x03C4, 0x00, 0x00),
MX91_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x0228, 0x0078, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x0228, 0x0078, 0x01, 0x04F8, 0x00, 0x00),
MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 = IOMUX_PAD(0x0228, 0x0078, 0x02, 0x04C8, 0x01, 0x00),
MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x0228, 0x0078, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x0228, 0x0078, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x0228, 0x0078, 0x05, 0x03D8, 0x01, 0x00),
MX91_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x0228, 0x0078, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x0228, 0x0078, 0x07, 0x04E0, 0x00, 0x00),
MX91_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x022C, 0x007C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x022C, 0x007C, 0x01, 0x04FC, 0x00, 0x00),
MX91_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x022C, 0x007C, 0x02, 0x0364, 0x01, 0x00),
MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x022C, 0x007C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x022C, 0x007C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x022C, 0x007C, 0x05, 0x03DC, 0x01, 0x00),
MX91_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x022C, 0x007C, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x022C, 0x007C, 0x07, 0x03C8, 0x00, 0x00),
MX91_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x0230, 0x0080, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x0230, 0x0080, 0x01, 0x03F4, 0x01, 0x00),
MX91_PAD_GPIO_IO28__CAN1_TX = IOMUX_PAD(0x0230, 0x0080, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x0230, 0x0080, 0x07, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x0234, 0x0084, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x0234, 0x0084, 0x01, 0x03F0, 0x01, 0x00),
MX91_PAD_GPIO_IO29__CAN1_RX = IOMUX_PAD(0x0234, 0x0084, 0x02, 0x0360, 0x00, 0x00),
MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x0234, 0x0084, 0x07, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0238, 0x0088, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x0238, 0x0088, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x0238, 0x0088, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x023C, 0x008C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x023C, 0x008C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x023C, 0x008C, 0x04, 0x03C8, 0x01, 0x00),
MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x0240, 0x0090, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x0240, 0x0090, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x0240, 0x0090, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x0244, 0x0094, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x0244, 0x0094, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x0244, 0x0094, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__ENET1_MDC = IOMUX_PAD(0x0248, 0x0098, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x0248, 0x0098, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x0248, 0x0098, 0x02, 0x03CC, 0x00, 0x00),
MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x0248, 0x0098, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 = IOMUX_PAD(0x0248, 0x0098, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__GPIO4_IO0 = IOMUX_PAD(0x0248, 0x0098, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDC__LPI2C1_SCL = IOMUX_PAD(0x0248, 0x0098, 0x06, 0x03E0, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x024C, 0x009C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x024C, 0x009C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x024C, 0x009C, 0x02, 0x03D0, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x024C, 0x009C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 = IOMUX_PAD(0x024C, 0x009C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__GPIO4_IO1 = IOMUX_PAD(0x024C, 0x009C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_MDIO__LPI2C1_SDA = IOMUX_PAD(0x024C, 0x009C, 0x06, 0x03E4, 0x00, 0x00),
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x0250, 0x00A0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 = IOMUX_PAD(0x0250, 0x00A0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD3__GPIO4_IO3 = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD3__LPI2C2_SCL = IOMUX_PAD(0x0250, 0x00A0, 0x06, 0x03E8, 0x00, 0x00),
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK = IOMUX_PAD(0x0254, 0x00A4, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x0254, 0x00A4, 0x02, 0x0364, 0x02, 0x00),
MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x0254, 0x00A4, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 = IOMUX_PAD(0x0254, 0x00A4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD2__GPIO4_IO3 = IOMUX_PAD(0x0254, 0x00A4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD2__LPI2C2_SDA = IOMUX_PAD(0x0254, 0x00A4, 0x06, 0x03EC, 0x00, 0x00),
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x0258, 0x00A8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x0258, 0x00A8, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x0258, 0x00A8, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x0258, 0x00A8, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 = IOMUX_PAD(0x0258, 0x00A8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__GPIO4_IO4 = IOMUX_PAD(0x0258, 0x00A8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x0258, 0x00A8, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x025C, 0x00AC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x025C, 0x00AC, 0x01, 0x0474, 0x01, 0x00),
MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 = IOMUX_PAD(0x025C, 0x00AC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TD0__GPIO4_IO5 = IOMUX_PAD(0x025C, 0x00AC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x0260, 0x00B0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x0260, 0x00B0, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 = IOMUX_PAD(0x0260, 0x00B0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 = IOMUX_PAD(0x0260, 0x00B0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK = IOMUX_PAD(0x0260, 0x00B0, 0x02, 0x043C, 0x00, 0x00),
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x0264, 0x00B4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x0264, 0x00B4, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 = IOMUX_PAD(0x0264, 0x00B4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TXC__GPIO4_IO7 = IOMUX_PAD(0x0264, 0x00B4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_TXC__LPSPI2_SIN = IOMUX_PAD(0x0264, 0x00B4, 0x02, 0x0440, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x0268, 0x00B8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x0268, 0x00B8, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x0268, 0x00B8, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 = IOMUX_PAD(0x0268, 0x00B8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 = IOMUX_PAD(0x0268, 0x00B8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 = IOMUX_PAD(0x0268, 0x00B8, 0x02, 0x0434, 0x00, 0x00),
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC = IOMUX_PAD(0x026C, 0x00BC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x026C, 0x00BC, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 = IOMUX_PAD(0x026C, 0x00BC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RXC__GPIO4_IO9 = IOMUX_PAD(0x026C, 0x00BC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RXC__LPSPI2_SOUT = IOMUX_PAD(0x026C, 0x00BC, 0x02, 0x0444, 0x00, 0x00),
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x0270, 0x00C0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x0270, 0x00C0, 0x01, 0x0470, 0x01, 0x00),
MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x0270, 0x00C0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x0270, 0x00C0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x0274, 0x00C4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x0274, 0x00C4, 0x01, 0x046C, 0x01, 0x00),
MX91_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x0274, 0x00C4, 0x03, 0x0448, 0x00, 0x00),
MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x0274, 0x00C4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x0274, 0x00C4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x0278, 0x00C8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x0278, 0x00C8, 0x03, 0x044C, 0x00, 0x00),
MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x0278, 0x00C8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x0278, 0x00C8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x027C, 0x00CC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x027C, 0x00CC, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x027C, 0x00CC, 0x03, 0x0450, 0x00, 0x00),
MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x027C, 0x00CC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x027C, 0x00CC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__ENET2_MDC = IOMUX_PAD(0x0280, 0x00D0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x0280, 0x00D0, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x0280, 0x00D0, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x0280, 0x00D0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x0280, 0x00D0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x0280, 0x00D0, 0x06, 0x04BC, 0x01, 0x00),
MX91_PAD_ENET2_MDIO__ENET2_MDIO = IOMUX_PAD(0x0284, 0x00D4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x0284, 0x00D4, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x0284, 0x00D4, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x0284, 0x00D4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x0284, 0x00D4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 = IOMUX_PAD(0x0284, 0x00D4, 0x06, 0x0490, 0x01, 0x00),
MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 = IOMUX_PAD(0x0288, 0x00D8, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x0288, 0x00D8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x0288, 0x00D8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x0288, 0x00D8, 0x06, 0x04C0, 0x01, 0x00),
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 = IOMUX_PAD(0x0288, 0x00D8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 = IOMUX_PAD(0x028C, 0x00DC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 = IOMUX_PAD(0x028C, 0x00DC, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x028C, 0x00DC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x028C, 0x00DC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x028C, 0x00DC, 0x06, 0x04B8, 0x01, 0x00),
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 = IOMUX_PAD(0x0290, 0x00E0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x0290, 0x00E0, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x0290, 0x00E0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x0290, 0x00E0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 = IOMUX_PAD(0x0290, 0x00E0, 0x06, 0x0494, 0x01, 0x00),
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 = IOMUX_PAD(0x0294, 0x00E4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x0294, 0x00E4, 0x01, 0x0480, 0x01, 0x00),
MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x0294, 0x00E4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x0294, 0x00E4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 = IOMUX_PAD(0x0294, 0x00E4, 0x06, 0x0498, 0x01, 0x00),
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x0298, 0x00E8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x0298, 0x00E8, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x0298, 0x00E8, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x0298, 0x00E8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x0298, 0x00E8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 = IOMUX_PAD(0x0298, 0x00E8, 0x06, 0x049C, 0x01, 0x00),
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC = IOMUX_PAD(0x029C, 0x00EC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TXC__ENET2_TX_ER = IOMUX_PAD(0x029C, 0x00EC, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x029C, 0x00EC, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x029C, 0x00EC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x029C, 0x00EC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 = IOMUX_PAD(0x029C, 0x00EC, 0x06, 0x04A0, 0x01, 0x00),
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02A0, 0x00F0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x02A0, 0x00F0, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 = IOMUX_PAD(0x02A0, 0x00F0, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x02A0, 0x00F0, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x02A0, 0x00F0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 = IOMUX_PAD(0x02A0, 0x00F0, 0x06, 0x04A4, 0x01, 0x00),
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC = IOMUX_PAD(0x02A4, 0x00F4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RXC__ENET2_RX_ER = IOMUX_PAD(0x02A4, 0x00F4, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x02A4, 0x00F4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x02A4, 0x00F4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 = IOMUX_PAD(0x02A4, 0x00F4, 0x06, 0x04A8, 0x01, 0x00),
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 = IOMUX_PAD(0x02A8, 0x00F8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x02A8, 0x00F8, 0x01, 0x047C, 0x01, 0x00),
MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x02A8, 0x00F8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x02A8, 0x00F8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 = IOMUX_PAD(0x02A8, 0x00F8, 0x06, 0x04AC, 0x01, 0x00),
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 = IOMUX_PAD(0x02AC, 0x00FC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x02AC, 0x00FC, 0x01, 0x04E4, 0x01, 0x00),
MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x02AC, 0x00FC, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x02AC, 0x00FC, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 = IOMUX_PAD(0x02AC, 0x00FC, 0x06, 0x04B0, 0x01, 0x00),
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 = IOMUX_PAD(0x02B0, 0x0100, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x02B0, 0x0100, 0x01, 0x0478, 0x01, 0x00),
MX91_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x02B0, 0x0100, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x02B0, 0x0100, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x02B0, 0x0100, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x02B0, 0x0100, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 = IOMUX_PAD(0x02B0, 0x0100, 0x06, 0x04B4, 0x01, 0x00),
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 = IOMUX_PAD(0x02B4, 0x0104, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x02B4, 0x0104, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x02B4, 0x0104, 0x02, 0x04E4, 0x02, 0x00),
MX91_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x02B4, 0x0104, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x02B4, 0x0104, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x02B4, 0x0104, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 = IOMUX_PAD(0x02B8, 0x0108, 0x04, 0x038C, 0x01, 0x00),
MX91_PAD_SD1_CLK__GPIO3_IO8 = IOMUX_PAD(0x02B8, 0x0108, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02B8, 0x0108, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_CLK__LPSPI2_SCK = IOMUX_PAD(0x02B8, 0x0108, 0x03, 0x043C, 0x01, 0x00),
MX91_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02BC, 0x010C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 = IOMUX_PAD(0x02BC, 0x010C, 0x04, 0x0390, 0x01, 0x00),
MX91_PAD_SD1_CMD__GPIO3_IO9 = IOMUX_PAD(0x02BC, 0x010C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_CMD__LPSPI2_SIN = IOMUX_PAD(0x02BC, 0x010C, 0x03, 0x0440, 0x01, 0x00),
MX91_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02C0, 0x0110, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x02C0, 0x0110, 0x04, 0x0394, 0x01, 0x00),
MX91_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x02C0, 0x0110, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA0__LPSPI2_PCS0 = IOMUX_PAD(0x02C0, 0x0110, 0x03, 0x0434, 0x01, 0x00),
MX91_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02C4, 0x0114, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x02C4, 0x0114, 0x04, 0x0398, 0x01, 0x00),
MX91_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x02C4, 0x0114, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x02C4, 0x0114, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA1__LPSPI2_SOUT = IOMUX_PAD(0x02C4, 0x0114, 0x03, 0x0444, 0x01, 0x00),
MX91_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02C8, 0x0118, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x02C8, 0x0118, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x02C8, 0x0118, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02C8, 0x0118, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA2__LPSPI2_PCS1 = IOMUX_PAD(0x02C8, 0x0118, 0x03, 0x0438, 0x00, 0x00),
MX91_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x02CC, 0x011C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x02CC, 0x011C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x02CC, 0x011C, 0x04, 0x039C, 0x01, 0x00),
MX91_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x02CC, 0x011C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA3__LPSPI1_PCS1 = IOMUX_PAD(0x02CC, 0x011C, 0x03, 0x0424, 0x00, 0x00),
MX91_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 = IOMUX_PAD(0x02D0, 0x0120, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x02D0, 0x0120, 0x04, 0x03A0, 0x01, 0x00),
MX91_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x02D0, 0x0120, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA4__LPSPI1_PCS0 = IOMUX_PAD(0x02D0, 0x0120, 0x03, 0x0420, 0x00, 0x00),
MX91_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 = IOMUX_PAD(0x02D4, 0x0124, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x02D4, 0x0124, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x02D4, 0x0124, 0x04, 0x03A4, 0x01, 0x00),
MX91_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x02D4, 0x0124, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA5__LPSPI1_SIN = IOMUX_PAD(0x02D4, 0x0124, 0x03, 0x042C, 0x00, 0x00),
MX91_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 = IOMUX_PAD(0x02D8, 0x0128, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x02D8, 0x0128, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x02D8, 0x0128, 0x04, 0x03A8, 0x01, 0x00),
MX91_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x02D8, 0x0128, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA6__LPSPI1_SCK = IOMUX_PAD(0x02D8, 0x0128, 0x03, 0x0428, 0x00, 0x00),
MX91_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 = IOMUX_PAD(0x02DC, 0x012C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x02DC, 0x012C, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x02DC, 0x012C, 0x04, 0x03AC, 0x01, 0x00),
MX91_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x02DC, 0x012C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_DATA7__LPSPI1_SOUT = IOMUX_PAD(0x02DC, 0x012C, 0x03, 0x0430, 0x00, 0x00),
MX91_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x02E0, 0x0130, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x02E0, 0x0130, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x02E0, 0x0130, 0x04, 0x03B0, 0x01, 0x00),
MX91_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x02E0, 0x0130, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x02E4, 0x0134, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x02E4, 0x0134, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x02E4, 0x0134, 0x02, 0x0450, 0x01, 0x00),
MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x02E4, 0x0134, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x02E4, 0x0134, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x02E4, 0x0134, 0x06, 0x0368, 0x00, 0x00),
MX91_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x02E8, 0x0138, 0x00, 0x04E8, 0x01, 0x00),
MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x02E8, 0x0138, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_CLK__LPUART1_CTS_B = IOMUX_PAD(0x02E8, 0x0138, 0x02, 0x0454, 0x00, 0x00),
MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x02E8, 0x0138, 0x04, 0x03B4, 0x01, 0x00),
MX91_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x02E8, 0x0138, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x02EC, 0x013C, 0x00, 0x04EC, 0x01, 0x00),
MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x02EC, 0x013C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_CMD__LPUART1_RTS_B = IOMUX_PAD(0x02EC, 0x013C, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x02EC, 0x013C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x02EC, 0x013C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0x00, 0x04F0, 0x01, 0x00),
MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 = IOMUX_PAD(0x02F0, 0x0140, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA0__LPUART2_CTS_B = IOMUX_PAD(0x02F0, 0x0140, 0x02, 0x0460, 0x00, 0x00),
MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x02F0, 0x0140, 0x04, 0x03B8, 0x01, 0x00),
MX91_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x02F0, 0x0140, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0x00, 0x04F4, 0x01, 0x00),
MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 = IOMUX_PAD(0x02F4, 0x0144, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA1__LPUART2_RTS_B = IOMUX_PAD(0x02F4, 0x0144, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x02F4, 0x0144, 0x04, 0x03BC, 0x01, 0x00),
MX91_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x02F4, 0x0144, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0x00, 0x04F8, 0x01, 0x00),
MX91_PAD_SD3_DATA2__LPI2C4_SDA = IOMUX_PAD(0x02F8, 0x0148, 0x02, 0x03FC, 0x01, 0x00),
MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 = IOMUX_PAD(0x02F8, 0x0148, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x02F8, 0x0148, 0x04, 0x03C0, 0x01, 0x00),
MX91_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x02F8, 0x0148, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0x00, 0x04FC, 0x01, 0x00),
MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 = IOMUX_PAD(0x02FC, 0x014C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD3_DATA3__LPI2C4_SCL = IOMUX_PAD(0x02FC, 0x014C, 0x02, 0x03F8, 0x01, 0x00),
MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x02FC, 0x014C, 0x04, 0x03C4, 0x01, 0x00),
MX91_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x02FC, 0x014C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x0300, 0x0150, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0300, 0x0150, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x0300, 0x0150, 0x02, 0x03CC, 0x01, 0x00),
MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 = IOMUX_PAD(0x0300, 0x0150, 0x04, 0x036C, 0x01, 0x00),
MX91_PAD_SD2_CD_B__GPIO3_IO0 = IOMUX_PAD(0x0300, 0x0150, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CD_B__LPI2C1_SCL = IOMUX_PAD(0x0300, 0x0150, 0x03, 0x03E0, 0x01, 0x00),
MX91_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0304, 0x0154, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0304, 0x0154, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CLK__I2C1_SDA = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x0304, 0x0154, 0x02, 0x03D0, 0x01, 0x00),
MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 = IOMUX_PAD(0x0304, 0x0154, 0x04, 0x0370, 0x01, 0x00),
MX91_PAD_SD2_CLK__GPIO3_IO1 = IOMUX_PAD(0x0304, 0x0154, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0304, 0x0154, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CLK__LPI2C1_SDA = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x03E4, 0x01, 0x00),
MX91_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0308, 0x0158, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0308, 0x0158, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x0308, 0x0158, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x0308, 0x0158, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 = IOMUX_PAD(0x0308, 0x0158, 0x04, 0x0374, 0x01, 0x00),
MX91_PAD_SD2_CMD__GPIO3_IO2 = IOMUX_PAD(0x0308, 0x0158, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0308, 0x0158, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x030C, 0x015C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x030C, 0x015C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x030C, 0x015C, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 = IOMUX_PAD(0x030C, 0x015C, 0x04, 0x0378, 0x01, 0x00),
MX91_PAD_SD2_DATA0__GPIO3_IO3 = IOMUX_PAD(0x030C, 0x015C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA0__LPUART1_TX = IOMUX_PAD(0x030C, 0x015C, 0x03, 0x045C, 0x00, 0x00),
MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x030C, 0x015C, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0310, 0x0160, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0310, 0x0160, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x0310, 0x0160, 0x02, 0x0364, 0x03, 0x00),
MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 = IOMUX_PAD(0x0310, 0x0160, 0x04, 0x037C, 0x01, 0x00),
MX91_PAD_SD2_DATA1__GPIO3_IO4 = IOMUX_PAD(0x0310, 0x0160, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA1__LPUART1_RX = IOMUX_PAD(0x0310, 0x0160, 0x03, 0x0458, 0x00, 0x00),
MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0310, 0x0160, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0314, 0x0164, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x0314, 0x0164, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x0314, 0x0164, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 = IOMUX_PAD(0x0314, 0x0164, 0x04, 0x0380, 0x01, 0x00),
MX91_PAD_SD2_DATA2__GPIO3_IO5 = IOMUX_PAD(0x0314, 0x0164, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA2__LPUART2_TX = IOMUX_PAD(0x0314, 0x0164, 0x03, 0x0468, 0x00, 0x00),
MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0314, 0x0164, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0318, 0x0168, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x0318, 0x0168, 0x01, 0x0448, 0x01, 0x00),
MX91_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x0318, 0x0168, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 = IOMUX_PAD(0x0318, 0x0168, 0x04, 0x0384, 0x01, 0x00),
MX91_PAD_SD2_DATA3__GPIO3_IO6 = IOMUX_PAD(0x0318, 0x0168, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_DATA3__LPUART2_RX = IOMUX_PAD(0x0318, 0x0168, 0x03, 0x0464, 0x00, 0x00),
MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0318, 0x0168, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x031C, 0x016C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x031C, 0x016C, 0x01, 0x044C, 0x01, 0x00),
MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 = IOMUX_PAD(0x031C, 0x016C, 0x04, 0x0388, 0x01, 0x00),
MX91_PAD_SD2_RESET_B__GPIO3_IO7 = IOMUX_PAD(0x031C, 0x016C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x031C, 0x016C, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0x00, 0x03E0, 0x02, 0x00),
MX91_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x0320, 0x0170, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x0320, 0x0170, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x0320, 0x0170, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SCL__GPIO1_IO0 = IOMUX_PAD(0x0320, 0x0170, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0x00, 0x03E4, 0x02, 0x00),
MX91_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x0324, 0x0174, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x0324, 0x0174, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x0324, 0x0174, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_I2C1_SDA__GPIO1_IO1 = IOMUX_PAD(0x0324, 0x0174, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x0328, 0x0178, 0x00, 0x03E8, 0x01, 0x00),
MX91_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x0328, 0x0178, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__GPIO1_IO3 = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0x00, 0x03EC, 0x01, 0x00),
MX91_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x032C, 0x017C, 0x02, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x032C, 0x017C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x032C, 0x017C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_I2C2_SDA__GPIO1_IO3 = IOMUX_PAD(0x032C, 0x017C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x0330, 0x0180, 0x00, 0x0458, 0x01, 0x00),
MX91_PAD_UART1_RXD__ELE_UART_RX = IOMUX_PAD(0x0330, 0x0180, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x0330, 0x0180, 0x02, 0x0440, 0x02, 0x00),
MX91_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x0330, 0x0180, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_RXD__GPIO1_IO4 = IOMUX_PAD(0x0330, 0x0180, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x0334, 0x0184, 0x00, 0x045C, 0x01, 0x00),
MX91_PAD_UART1_TXD__ELE_UART_TX = IOMUX_PAD(0x0334, 0x0184, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x0334, 0x0184, 0x02, 0x0434, 0x02, 0x00),
MX91_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x0334, 0x0184, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_UART1_TXD__GPIO1_IO5 = IOMUX_PAD(0x0334, 0x0184, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x0338, 0x0188, 0x00, 0x0464, 0x01, 0x00),
MX91_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x0338, 0x0188, 0x01, 0x0454, 0x01, 0x00),
MX91_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x0338, 0x0188, 0x02, 0x0444, 0x02, 0x00),
MX91_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x0338, 0x0188, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x0338, 0x0188, 0x04, 0x04D4, 0x00, 0x00),
MX91_PAD_UART2_RXD__GPIO1_IO6 = IOMUX_PAD(0x0338, 0x0188, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x033C, 0x018C, 0x00, 0x0468, 0x01, 0x00),
MX91_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x033C, 0x018C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x033C, 0x018C, 0x02, 0x043C, 0x02, 0x00),
MX91_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x033C, 0x018C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_TXD__GPIO1_IO7 = IOMUX_PAD(0x033C, 0x018C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_UART2_TXD__SAI3_TX_SYNC = IOMUX_PAD(0x033C, 0x018C, 0x07, 0x04E0, 0x02, 0x00),
MX91_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x0340, 0x0190, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x0340, 0x0190, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x0340, 0x0190, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_CLK__GPIO1_IO8 = IOMUX_PAD(0x0340, 0x0190, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x0340, 0x0190, 0x06, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 = IOMUX_PAD(0x0344, 0x0194, 0x00, 0x04C4, 0x02, 0x00),
MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x0344, 0x0194, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x0344, 0x0194, 0x02, 0x0424, 0x01, 0x00),
MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x0344, 0x0194, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x0344, 0x0194, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 = IOMUX_PAD(0x0344, 0x0194, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x0344, 0x0194, 0x06, 0x0360, 0x01, 0x00),
MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 = IOMUX_PAD(0x0348, 0x0198, 0x00, 0x04C8, 0x02, 0x00),
MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x0348, 0x0198, 0x02, 0x0438, 0x01, 0x00),
MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x0348, 0x0198, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x0348, 0x0198, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x0348, 0x0198, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0348, 0x0198, 0x06, 0x0368, 0x01, 0x00),
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x034C, 0x019C, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 = IOMUX_PAD(0x034C, 0x019C, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x034C, 0x019C, 0x02, 0x0420, 0x01, 0x00),
MX91_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x034C, 0x019C, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x034C, 0x019C, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x034C, 0x019C, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x0350, 0x01A0, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x0350, 0x01A0, 0x01, 0x0460, 0x01, 0x00),
MX91_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x0350, 0x01A0, 0x02, 0x042C, 0x01, 0x00),
MX91_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x0350, 0x01A0, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x0350, 0x01A0, 0x04, 0x0360, 0x02, 0x00),
MX91_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x0350, 0x01A0, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 = IOMUX_PAD(0x0354, 0x01A4, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x0354, 0x01A4, 0x01, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x0354, 0x01A4, 0x02, 0x0428, 0x01, 0x00),
MX91_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x0354, 0x01A4, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x0354, 0x01A4, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x0354, 0x01A4, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_TXD0__SAI1_MCLK = IOMUX_PAD(0x0354, 0x01A4, 0x06, 0x04D4, 0x01, 0x00),
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 = IOMUX_PAD(0x0358, 0x01A8, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x0358, 0x01A8, 0x01, 0x04D4, 0x02, 0x00),
MX91_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x0358, 0x01A8, 0x02, 0x0430, 0x01, 0x00),
MX91_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x0358, 0x01A8, 0x03, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x0358, 0x01A8, 0x04, 0x0000, 0x00, 0x00),
MX91_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x0358, 0x01A8, 0x05, 0x0000, 0x00, 0x00),
MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x035C, 0x01AC, 0x00, 0x0000, 0x00, 0x00),
MX91_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x035C, 0x01AC, 0x05, 0x0000, 0x00, 0x00),
};
#endif /* __ASM_ARCH_IMX91_PINS_H__ */

2
arch/arm/include/asm/mach-imx/iomux-v3.h
View file

@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_IMX93
#if defined(CONFIG_IMX93) || defined(CONFIG_IMX91)
#define PAD_CTL_FSEL2 (0x2 << 7)
#define PAD_CTL_FSEL3 (0x3 << 7)
#define PAD_CTL_PUE (0x1 << 9)

6
arch/arm/include/asm/mach-imx/sys_proto.h
View file

@ -97,6 +97,12 @@ struct bd_info;
#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
#define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
#define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
#define is_imx91() (is_cpu_type(MXC_CPU_IMX91) || is_cpu_type(MXC_CPU_IMX9111) || \
is_cpu_type(MXC_CPU_IMX9101) || is_cpu_type(MXC_CPU_IMX9121))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))

13
arch/arm/mach-imx/imx9/Kconfig
View file

@ -16,6 +16,12 @@ config IMX93
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
config IMX91
bool
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
config SYS_SOC
default "imx9"
@ -23,6 +29,12 @@ choice
prompt "NXP i.MX9 board select"
optional
config TARGET_IMX91_11X11_EVK
bool "imx91_11x11_evk"
select OF_BOARD_FIXUP
select IMX91
imply OF_UPSTREAM
config TARGET_IMX93_9X9_QSB
bool "imx93_qsb"
select OF_BOARD_FIXUP
@ -50,6 +62,7 @@ config TARGET_PHYCORE_IMX93
endchoice
source "board/freescale/imx91_evk/Kconfig"
source "board/freescale/imx93_evk/Kconfig"
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"

37
arch/arm/mach-imx/imx9/clock.c
View file

@ -30,6 +30,7 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
INT_PLL_RATE(800000000U, 1, 200, 6), /* 800Mhz */
};
static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
@ -37,12 +38,14 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
FRAC_PLL_RATE(200000000U, 1, 200, 24, 0, 1), /* 200Mhz */
};
/* return in khz */
@ -723,7 +726,7 @@ struct imx_clk_setting imx_clk_ld_settings[] = {
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
/* NIC to 250M */
{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
/* NIC_APB to 133M */
@ -753,13 +756,17 @@ struct imx_clk_setting imx_clk_settings[] = {
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M
*/
{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2, CLK_SOC_IMX93},
/* Wakeup AXI 250M*/
{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD0, 4, CLK_SOC_IMX91},
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
/* NIC to 400M */
{NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
{NIC_CLK_ROOT, SYS_PLL_PFD1, 2, CLK_SOC_IMX93},
/* NIC to 333M */
{NIC_CLK_ROOT, SYS_PLL_PFD0, 3, CLK_SOC_IMX91},
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
@ -769,8 +776,12 @@ void bus_clock_init_low_drive(void)
int i;
for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
if (imx_clk_ld_settings[i].soc == CLK_SOC_ALL ||
(is_imx91() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX91) ||
(is_imx93() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX93)) {
ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
}
}
}
@ -779,8 +790,12 @@ void bus_clock_init(void)
int i;
for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src, imx_clk_settings[i].div);
if (imx_clk_settings[i].soc == CLK_SOC_ALL ||
(is_imx91() && imx_clk_settings[i].soc == CLK_SOC_IMX91) ||
(is_imx93() && imx_clk_settings[i].soc == CLK_SOC_IMX93)) {
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src, imx_clk_settings[i].div);
}
}
}
@ -857,7 +872,7 @@ u32 imx_get_fecclk(void)
return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
}
#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS)
#if (CONFIG_IS_ENABLED(IMX93) || CONFIG_IS_ENABLED(IMX91)) && CONFIG_IS_ENABLED(DWC_ETH_QOS)
static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
{
struct blk_ctrl_wakeupmix_regs *bctrl =
@ -901,12 +916,12 @@ static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interf
int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
{
if (IS_ENABLED(CONFIG_IMX93) &&
if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
return imx93_eqos_interface_init(dev, interface_type);
if (IS_ENABLED(CONFIG_IMX93) &&
if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx93-fec"))
return 0;

6
arch/arm/mach-imx/imx9/container.cfg
View file

@ -6,6 +6,10 @@
BOOT_FROM SD 0x400
SOC_TYPE IMX9
CONTAINER
#ifdef CONFIG_IMX91
IMAGE A55 bl31.bin 0x204C0000
#else
IMAGE A55 bl31.bin 0x204E0000
#endif
IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
IMAGE A55 tee.bin 0x96000000
IMAGE A55 tee.bin 0x96000000

6
arch/arm/mach-imx/imx9/imximage.cfg
View file

@ -5,6 +5,10 @@
BOOT_FROM SD 0x400
SOC_TYPE IMX9
#ifdef CONFIG_IMX91
APPEND mx91a0-ahab-container.img
#else
APPEND mx93a1-ahab-container.img
#endif
CONTAINER
IMAGE A55 u-boot-spl-ddr.bin 0x2049A000
IMAGE A55 u-boot-spl-ddr.bin CONFIG_SPL_TEXT_BASE

47
arch/arm/mach-imx/imx9/soc.c
View file

@ -118,6 +118,8 @@ u32 get_cpu_speed_grade_hz(void)
if (is_imx93())
max_speed = MHZ(1700);
else if (is_imx91())
max_speed = MHZ(1400);
/* In case the fuse of speed grade not programmed */
if (speed > max_speed)
@ -195,7 +197,30 @@ static u32 get_cpu_variant_type(u32 type)
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
/* For iMX91 */
if (type == MXC_CPU_IMX91) {
switch (nxp_recog) {
case 0x9:
case 0xA:
type = MXC_CPU_IMX9111;
break;
case 0xD:
case 0xE:
type = MXC_CPU_IMX9121;
break;
case 0xF:
case 0x10:
type = MXC_CPU_IMX9101;
break;
default:
break; /* 9131 as default */
}
return type;
}
/* Low performance 93 part */
if (((val >> 6) & 0x3F) == 0xE && npu_disable)
@ -217,8 +242,14 @@ static u32 get_cpu_variant_type(u32 type)
u32 get_cpu_rev(void)
{
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
u32 type;
return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
if ((gd->arch.soc_rev & 0xFFFF) == 0x9300)
type = MXC_CPU_IMX93;
else
type = MXC_CPU_IMX91;
return (get_cpu_variant_type(type) << 12) |
(CHIP_REV_1_0 + rev);
}
@ -539,7 +570,8 @@ int print_cpuinfo(void)
cpurev = get_cpu_rev();
printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
printf("CPU: i.MX%s rev%d.%d\n", is_imx93() ? "93" : "91",
(cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
return 0;
}
@ -893,7 +925,9 @@ void disable_isolation(void)
void soc_power_init(void)
{
mix_power_init(MIX_PD_MEDIAMIX);
mix_power_init(MIX_PD_MLMIX);
if (is_imx93())
mix_power_init(MIX_PD_MLMIX);
disable_isolation();
}
@ -919,6 +953,9 @@ int m33_prepare(void)
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
u32 val, i;
if (is_imx91())
return -ENODEV;
if (m33_is_rom_kicked())
return -EPERM;
@ -1007,7 +1044,7 @@ enum imx9_soc_voltage_mode soc_target_voltage_mode(void)
u32 speed = get_cpu_speed_grade_hz();
enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
if (is_imx93()) {
if (is_imx93() || is_imx91()) {
if (speed == 1700000000)
voltage = VOLT_OVER_DRIVE;
else if (speed == 1400000000)

2
arch/arm/mach-imx/imx9/trdc.c
View file

@ -484,7 +484,7 @@ void trdc_init(void)
}
}
#if DEBUG
#ifdef DEBUG
int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);

166
board/dhelectronics/common/dh_common.c
View file

@ -7,9 +7,27 @@
#include <dm.h>
#include <i2c_eeprom.h>
#include <net.h>
#include <u-boot/crc.h>
#include "dh_common.h"
static int on_dh_som_serial_number(const char *name, const char *value, enum env_op op,
int flags)
{
env_set("SN", value);
return 0;
}
U_BOOT_ENV_CALLBACK(dh_som_serial_number, on_dh_som_serial_number);
static int on_SN(const char *name, const char *value, enum env_op op, int flags)
{
env_set("dh_som_serial_number", value);
return 0;
}
U_BOOT_ENV_CALLBACK(SN, on_SN);
bool dh_mac_is_in_env(const char *env)
{
unsigned char enetaddr[6];
@ -30,6 +48,149 @@ int dh_get_mac_is_enabled(const char *alias)
return 0;
}
int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias)
{
struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
struct udevice *dev;
size_t payload_len;
int eeprom_size;
u16 crc16_calc;
u16 crc16_eip;
u8 crc8_calc;
ofnode node;
int ret;
node = ofnode_path(alias);
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
if (ret)
return ret;
eeprom_size = i2c_eeprom_size(dev);
if (eeprom_size < 0) {
printf("%s: Error getting EEPROM ID page size! ret = %d\n", __func__, ret);
return eeprom_size;
}
if (eeprom_size == 0 || eeprom_size > DH_EEPROM_ID_PAGE_MAX_SIZE) {
eeprom_size = DH_EEPROM_ID_PAGE_MAX_SIZE;
printf("Get invalid EEPROM ID page size %d bytes! Try to read %d bytes.\n",
eeprom_size, DH_EEPROM_ID_PAGE_MAX_SIZE);
}
ret = i2c_eeprom_read(dev, 0x0, eeprom_buffer, eeprom_size);
if (ret) {
printf("%s: Error reading EEPROM ID page! ret = %d\n", __func__, ret);
return ret;
}
/* Validate header ID */
if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') {
printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n",
__func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.',
isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.',
isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.',
eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]);
return -EINVAL;
}
/* Validate header checksum */
crc8_calc = crc8(0xff, eeprom_buffer, offsetof(struct eeprom_id_page, hdr.crc8_hdr));
if (eip->hdr.crc8_hdr != crc8_calc) {
printf("%s: Error validating header checksum! (got 0x%02x != calc 0x%02x)\n",
__func__, eip->hdr.crc8_hdr, crc8_calc);
return -EINVAL;
}
/*
* Validate header version
* The payload is defined by the version specified in the header.
* Currently only version 0x10 is defined, so take the length of
* the only defined payload as the payload length.
*/
if (eip->hdr.version != DH_EEPROM_ID_PAGE_V1_0) {
printf("%s: Error validating version! (0x%02X is not supported)\n",
__func__, eip->hdr.version);
return -EINVAL;
}
payload_len = sizeof(eip->pl);
/* Validate payload checksum */
crc16_eip = (eip->hdr.crc16_pl[1] << 8) | eip->hdr.crc16_pl[0];
crc16_calc = crc16(0xffff, eeprom_buffer + sizeof(eip->hdr), payload_len);
if (crc16_eip != crc16_calc) {
printf("%s: Error validating data checksum! (got 0x%02x != calc 0x%02x)\n",
__func__, crc16_eip, crc16_calc);
return -EINVAL;
}
return 0;
}
int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
struct eeprom_id_page *eip)
{
const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ?
DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR;
const u8 soc_coded = eip->pl.item_prefix & 0xf;
char soc_chr;
if (!eip)
return -EINVAL;
/* Copy requested data */
switch (request) {
case DH_MAC0:
if (!is_valid_ethaddr(eip->pl.mac0))
return -EINVAL;
if (data_len >= sizeof(eip->pl.mac0))
memcpy(data, eip->pl.mac0, sizeof(eip->pl.mac0));
else
return -EINVAL;
break;
case DH_MAC1:
if (!is_valid_ethaddr(eip->pl.mac1))
return -EINVAL;
if (data_len >= sizeof(eip->pl.mac1))
memcpy(data, eip->pl.mac1, sizeof(eip->pl.mac1));
else
return -EINVAL;
break;
case DH_ITEM_NUMBER:
if (data_len < 8) /* String length must be 7 characters + string termination */
return -EINVAL;
if (soc_coded == DH_ITEM_PREFIX_NXP)
soc_chr = DH_ITEM_PREFIX_NXP_CHR;
else if (soc_coded == DH_ITEM_PREFIX_ST)
soc_chr = DH_ITEM_PREFIX_ST_CHR;
else
return -EINVAL;
snprintf(data, data_len, "%c%c%05d", fin_chr, soc_chr,
(eip->pl.item_num[0] << 16) | (eip->pl.item_num[1] << 8) |
eip->pl.item_num[2]);
break;
case DH_SERIAL_NUMBER:
/*
* data_len must be greater than the size of eip->pl.serial,
* because there is a string termination needed.
*/
if (data_len <= sizeof(eip->pl.serial))
return -EINVAL;
data[sizeof(eip->pl.serial)] = 0;
memcpy(data, eip->pl.serial, sizeof(eip->pl.serial));
break;
default:
return -EINVAL;
}
return 0;
}
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
{
struct udevice *dev;
@ -62,7 +223,7 @@ int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
return 0;
}
__weak int dh_setup_mac_address(void)
__weak int dh_setup_mac_address(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@ -72,6 +233,9 @@ __weak int dh_setup_mac_address(void)
if (dh_get_mac_is_enabled("ethernet0"))
return 0;
if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
return eth_env_set_enetaddr("ethaddr", enetaddr);
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
return eth_env_set_enetaddr("ethaddr", enetaddr);

79
board/dhelectronics/common/dh_common.h
View file

@ -3,6 +3,52 @@
* Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
*/
#define DH_EEPROM_ID_PAGE_MAX_SIZE 64
enum eip_request_values {
DH_MAC0,
DH_MAC1,
DH_ITEM_NUMBER,
DH_SERIAL_NUMBER,
};
/* DH item: Vendor coding */
#define DH_ITEM_PREFIX_NXP 0x01
#define DH_ITEM_PREFIX_NXP_CHR 'I'
#define DH_ITEM_PREFIX_ST 0x02
#define DH_ITEM_PREFIX_ST_CHR 'S'
/*
* DH item: Finished state coding
* Bit = 0 means half finished
* Prefix is 'H'
* Bit = 1 means finished with a customer image flashed
* Prefix is 'F'
*/
#define DH_ITEM_PREFIX_FIN_BIT BIT(7)
#define DH_ITEM_PREFIX_FIN_HALF_CHR 'H'
#define DH_ITEM_PREFIX_FIN_FLASHED_CHR 'F'
struct eeprom_id_page {
/* Header */
struct {
u8 id[3]; /* Identifier 'D', 'H', 'E' - 'D' is at index 0 */
u8 version; /* 0x10 -- Version 1.0 */
u8 crc16_pl[2]; /* Checksum payload, [1] is MSbyte */
u8 crc8_hdr; /* Checksum header */
} hdr;
/* Payload */
struct {
u8 mac0[6];
u8 mac1[6];
u8 item_prefix; /* H/F is coded in MSbits, Vendor coding starts at LSbits */
u8 item_num[3]; /* [2] is MSbyte */
u8 serial[9]; /* [8] is MSbyte */
} pl;
};
#define DH_EEPROM_ID_PAGE_V1_0 0x10
/*
* dh_mac_is_in_env - Check if MAC address is already set
*
@ -28,9 +74,40 @@ int dh_get_mac_is_enabled(const char *alias);
*/
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
/*
* dh_read_eeprom_id_page() - Read EEPROM ID page content into given buffer
* @eeprom_buffer: Buffer for EEPROM ID page content
* @alias: Alias for EEPROM ID page device tree node
*
* Read the content of the EEPROM ID page into the given buffer (parameter
* eeprom_buffer). The EEPROM ID page device is selected via alias device
* tree name (parameter alias). The data of the EEPROM ID page is verified.
* An error is returned for reading failures and invalid data.
*
* Return: 0 if OK, other value on error
*/
int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias);
/*
* dh_get_value_from_eeprom_buffer() - Get value from EEPROM buffer
* @eip_request_values: Requested value as enum
* @data: Buffer where value is to be stored
* @data_len: Length of the value buffer
* @eip: Pointer to EEPROM ID page struct from which the data is parsed
*
* Gets the value specified by the parameter eip_request_values from the EEPROM
* data struct (parameter eip). The data is written to the specified data
* buffer (parameter data). If the length of the data (parameter data_len) is
* not sufficient to copy the data into the buffer, an error is returned.
*
* Return: 0 if OK, other value on error
*/
int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len,
struct eeprom_id_page *eip);
/*
* dh_setup_mac_address - Try to get MAC address from various locations and write it to env
*
* Return: 0 if OK, other value on error
*/
int dh_setup_mac_address(void);
int dh_setup_mac_address(struct eeprom_id_page *eip);

4
board/dhelectronics/dh_imx6/dh_imx6.c
View file

@ -84,7 +84,7 @@ int board_usb_phy_mode(int port)
}
#endif
int dh_setup_mac_address(void)
int dh_setup_mac_address(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@ -171,7 +171,7 @@ int board_late_init(void)
u32 hw_code;
char buf[16];
dh_setup_mac_address();
dh_setup_mac_address(NULL);
hw_code = board_get_hwcode();

75
board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
View file

@ -40,7 +40,7 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
static int dh_imx8_setup_ethaddr(void)
static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@ -53,6 +53,9 @@ static int dh_imx8_setup_ethaddr(void)
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto out;
if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip))
goto out;
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
goto out;
@ -62,7 +65,7 @@ out:
return eth_env_set_enetaddr("ethaddr", enetaddr);
}
static int dh_imx8_setup_eth1addr(void)
static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip)
{
unsigned char enetaddr[6];
@ -75,6 +78,9 @@ static int dh_imx8_setup_eth1addr(void)
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto increment_out;
if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip))
goto out;
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
goto out;
@ -95,21 +101,58 @@ out:
return eth_env_set_enetaddr("eth1addr", enetaddr);
}
int dh_setup_mac_address(void)
int dh_setup_mac_address(struct eeprom_id_page *eip)
{
int ret;
ret = dh_imx8_setup_ethaddr();
ret = dh_imx8_setup_ethaddr(eip);
if (ret)
printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
ret = dh_imx8_setup_eth1addr();
ret = dh_imx8_setup_eth1addr(eip);
if (ret)
printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
return ret;
}
void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip)
{
char *item_number_env;
char item_number[8]; /* String with 7 characters + string termination */
char *serial_env;
char serial[10]; /* String with 9 characters + string termination */
int ret;
ret = dh_get_value_from_eeprom_buffer(DH_ITEM_NUMBER, item_number, sizeof(item_number),
eip);
if (ret) {
printf("%s: Unable to get DHSOM item number from EEPROM ID page! ret = %d\n",
__func__, ret);
} else {
item_number_env = env_get("dh_som_item_number");
if (!item_number_env)
env_set("dh_som_item_number", item_number);
else if (strcmp(item_number_env, item_number))
printf("Warning: Environment dh_som_item_number differs from EEPROM ID page value (%s != %s)\n",
item_number_env, item_number);
}
ret = dh_get_value_from_eeprom_buffer(DH_SERIAL_NUMBER, serial, sizeof(serial),
eip);
if (ret) {
printf("%s: Unable to get DHSOM serial number from EEPROM ID page! ret = %d\n",
__func__, ret);
} else {
serial_env = env_get("dh_som_serial_number");
if (!serial_env)
env_set("dh_som_serial_number", serial);
else if (strcmp(serial_env, serial))
printf("Warning: Environment dh_som_serial_number differs from EEPROM ID page value (%s != %s)\n",
serial_env, serial);
}
}
int board_init(void)
{
return 0;
@ -117,7 +160,27 @@ int board_init(void)
int board_late_init(void)
{
dh_setup_mac_address();
u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 };
struct eeprom_id_page *eip = (struct eeprom_id_page *)eeprom_buffer;
int ret;
ret = dh_read_eeprom_id_page(eeprom_buffer, "eeprom0wl");
if (ret) {
/*
* The EEPROM ID page is available on SoM rev. 200 and greater.
* For SoM rev. 100 the return value will be -ENODEV. Suppress
* the error message for that, because the absence cannot be
* treated as an error.
*/
if (ret != -ENODEV)
printf("%s: Cannot read valid data from EEPROM ID page! ret = %d\n",
__func__, ret);
dh_setup_mac_address(NULL);
} else {
dh_setup_mac_address(eip);
dh_add_item_number_and_serial_to_env(eip);
}
return 0;
}

19
board/freescale/imx91_evk/Kconfig Normal file
View file

@ -0,0 +1,19 @@
if TARGET_IMX91_11X11_EVK
config SYS_BOARD
default "imx91_evk"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx91_evk"
config IMX91_EVK_LPDDR4
bool "Using LPDDR4 Timing and PMIC voltage"
default y
select IMX9_LPDDR4X
help
Select the LPDDR4 timing and 1.1V VDDQ
endif

7
board/freescale/imx91_evk/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
i.MX91 11x11 EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx91_evk/
F: include/configs/imx91_evk.h
F: configs/imx91_11x11_evk_defconfig
F: configs/imx91_11x11_evk_inline_ecc_defconfig

16
board/freescale/imx91_evk/Makefile Normal file
View file

@ -0,0 +1,16 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx91_evk.o
ifdef CONFIG_XPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX9_DRAM_INLINE_ECC
obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o
else
obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o
endif
endif

33
board/freescale/imx91_evk/imx91_evk.c Normal file
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@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*/
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
int board_init(void)
{
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
env_set("sec_boot", "no");
#ifdef CONFIG_AHAB_BOOT
env_set("sec_boot", "yes");
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "11X11_EVK");
env_set("board_rev", "iMX93");
#endif
return 0;
}

63
board/freescale/imx91_evk/imx91_evk.env Normal file
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@ -0,0 +1,63 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
boot_targets=mmc0 mmc1
boot_fit=no
bootm_size=0x10000000
cntr_addr=0x98000000
cntr_file=os_cntr_signed.bin
console=ttyLP0,115200 earlycon
fdt_addr_r=0x83000000
fdt_addr=0x83000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
image=Image
mmcpart=1
mmcroot=/dev/mmcblk1p2 rootwait rw
mmcautodetect=yes
mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}
prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
auth_os=auth_cntr ${cntr_addr}
boot_os=booti ${loadaddr} - ${fdt_addr_r}
mmcboot=
echo Booting from mmc ...;
run mmcargs;
if test ${sec_boot} = yes; then
if run auth_os; then
run boot_os;
else
echo ERR: failed to authenticate;
fi;
else
if run loadfdt; then
run boot_os;
else
echo WARN: Cannot load the DT;
fi;
fi;
netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs
ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=
echo Booting from net ...;
run netargs;
if test ${ip_dyn} = yes; then
setenv get_cmd dhcp;
else
setenv get_cmd tftp;
fi;
if test ${sec_boot} = yes; then
${get_cmd} ${cntr_addr} ${cntr_file};
if run auth_os; then
run boot_os;
else
echo ERR: failed to authenticate;
fi;
else
${get_cmd} ${loadaddr} ${image};
if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
run boot_os;
else
echo WARN: Cannot load the DT;
fi;
fi;

1995
board/freescale/imx91_evk/lpddr4_timing_1600mts.c Normal file
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File diff suppressed because it is too large Load diff

1995
board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c Normal file
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File diff suppressed because it is too large Load diff

1995
board/freescale/imx91_evk/lpddr4_timing_2400mts.c Normal file
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File diff suppressed because it is too large Load diff

1995
board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c Normal file
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File diff suppressed because it is too large Load diff

167
board/freescale/imx91_evk/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*/
#include <command.h>
#include <cpu_func.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/mu.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <asm/arch/ccm_regs.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <asm/arch/trdc.h>
DECLARE_GLOBAL_DATA_PTR;
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_board_init(void)
{
int ret;
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
puts("Normal Boot\n");
}
extern struct dram_timing_info dram_timing_1600mts;
void spl_dram_init(void)
{
struct dram_timing_info *ptiming = &dram_timing;
if (is_voltage_mode(VOLT_LOW_DRIVE))
ptiming = &dram_timing_1600mts;
printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
ddr_init(ptiming);
}
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
int power_init_board(void)
{
struct udevice *dev;
int ret;
unsigned int val = 0, buck_val;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("ERROR: Get PMIC PCA9451A failed!\n");
return ret;
}
if (ret != 0)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
if (ret < 0)
return ret;
val = ret;
if (is_voltage_mode(VOLT_LOW_DRIVE)) {
buck_val = 0x0c; /* 0.8V for Low drive mode */
printf("PMIC: Low Drive Voltage Mode\n");
} else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
buck_val = 0x10; /* 0.85V for Nominal drive mode */
printf("PMIC: Nominal Voltage Mode\n");
} else {
buck_val = 0x14; /* 0.9V for Over drive mode */
printf("PMIC: Over Drive Voltage Mode\n");
}
if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
} else {
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
}
/* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
/* set standby voltage to 0.65V */
if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
else
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
timer_init();
arch_cpu_init();
spl_early_init();
preloader_console_init();
ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
debug("SOC: 0x%x\n", gd->arch.soc_rev);
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
clock_init_late();
power_init_board();
if (!is_voltage_mode(VOLT_LOW_DRIVE))
set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
soc_power_init();
/* Setup TRDC for DDR access */
trdc_init();
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

65
board/phytec/phycore_imx8mm/phycore_imx8mm.env Normal file
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@ -0,0 +1,65 @@
#include <env/phytec/rauc.env>
bootcmd=
mmc dev ${mmcdev};
if mmc rescan; then
if test ${doraucboot} = 1; then
run raucinit;
fi;
if run loadimage; then
run mmcboot;
else
run netboot;
fi;
fi;
console=ttymxc2,115200
emmc_dev=2
fdt_addr_r=0x48000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
image=Image
ip_dyn=yes
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
mmcargs=
setenv bootargs console=${console}
root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
mmcautodetect=yes
mmcboot=
echo Booting from mmc ...;
run mmcargs;
if run loadfdt; then
if test ${dofitboot} = 1; then
booti ${loadaddr} - ${fdt_addr_r}
else
echo WARN: Cannot load the DT;
fi;
fi;
mmcdev=CONFIG_SYS_MMC_ENV_DEV
mmcpart=1
mmcroot=2
netargs=
setenv bootargs console=${console} root=/dev/nfs ip=dhcp
nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=
echo Booting from net ...;
if test ${ip_dyn} = yes; then
setenv get_cmd dhcp;
else
setenv get_cmd tftp;
fi;
${get_cmd} ${loadaddr} ${image};
run netargs;
if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
booti ${loadaddr} - ${fdt_addr_r};
else
echo WARN: Cannot load the DT;
fi;
nfsroot=/srv/nfs
update_bootimg=
mmc dev ${mmcdev};
if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then
setexpr fw_sz ${filesize} / 0x200;
mmc write ${loadaddr} ${update_offset} ${fw_sz};
fi;
update_filename=flash.bin
update_offset=0x42

1
configs/dhsom.config
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@ -49,6 +49,7 @@ CONFIG_CMD_UUID=y
CONFIG_CMD_WGET=y
CONFIG_CMD_XXD=y
CONFIG_CRC32_VERIFY=y
CONFIG_ENV_CALLBACK_LIST_STATIC="dh_som_serial_number:dh_som_serial_number,SN:SN,"
CONFIG_HASH_VERIFY=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_SHA1SUM_VERIFY=y

145
configs/imx91_11x11_evk_defconfig Normal file
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@ -0,0 +1,145 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SOURCE_FILE="imx91_evk"
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x204E0000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_TEXT_BASE=0x204A0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x20498000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SPL=y
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_CPU=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_ADC=y
CONFIG_ADC_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_ADP5585_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_ULP_WATCHDOG=y
CONFIG_WDT=y
CONFIG_SHA384=y
CONFIG_LZO=y
CONFIG_BZIP2=y

146
configs/imx91_11x11_evk_inline_ecc_defconfig Normal file
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@ -0,0 +1,146 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SOURCE_FILE="imx91_evk"
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-11x11-evk"
CONFIG_TARGET_IMX91_11X11_EVK=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x204E0000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_TEXT_BASE=0x204A0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x20498000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_SPL=y
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_REMAKE_ELF=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_CPU=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="eth1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_ADC=y
CONFIG_ADC_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_CPU=y
CONFIG_CPU_IMX=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000
CONFIG_IMX9_DRAM_INLINE_ECC=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_ADP5585_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
CONFIG_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_SYSRESET_PSCI=y
CONFIG_ULP_WATCHDOG=y
CONFIG_WDT=y
CONFIG_SHA384=y
CONFIG_LZO=y
CONFIG_BZIP2=y

2
configs/phycore-imx8mm_defconfig
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@ -31,8 +31,6 @@ CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074

70
doc/board/nxp/imx91_11x11_evk.rst Normal file
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@ -0,0 +1,70 @@
.. SPDX-License-Identifier: GPL-2.0+
imx91_11x11_EVK
=======================
U-Boot for the NXP i.MX91 11x11 EVK
Quick Start
-----------
- Get and Build the ARM Trusted firmware
- Get the DDR firmware
- Get ahab-container.img
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
--------------------------------------
Note: srctree is U-Boot source directory
Get ATF from: https://github.com/nxp-imx/imx-atf/
branch: lf_v2.10
.. code-block:: bash
$ unset LDFLAGS
$ make PLAT=imx91 bl31
$ cp build/imx91/release/bl31.bin $(srctree)
Get the DDR firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
$ chmod +x firmware-imx-8.21.bin
$ ./firmware-imx-8.21.bin
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Get ahab-container.img
---------------------------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin
$ chmod +x firmware-ele-imx-1.3.0-17945fc.bin
$ ./firmware-ele-imx-1.3.0-17945fc.bin
$ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree)
Build U-Boot
------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx91_11x11_evk_defconfig or imx91_11x11_evk_inline_ecc_defconfig
$ make
- Inline ECC is to enable DDR ECC feature with imx91_11x11_evk_inline_ecc_defconfig
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
Set Boot switch to SD boot

1
doc/board/nxp/index.rst
View file

@ -12,6 +12,7 @@ NXP Semiconductors
imx8mq_evk
imx8qxp_mek
imx8ulp_evk
imx91_11x11_evk
imx93_9x9_qsb
imx93_11x11_evk
imxrt1020-evk

5
drivers/clk/imx/clk-fracn-gppll.c
View file

@ -86,6 +86,7 @@ struct clk_fracn_gppll {
*/
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
PLL_FRACN_GP(600000000U, 200, 0, 1, 0, 8),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
@ -93,7 +94,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
PLL_FRACN_GP(200000000U, 200, 0, 1, 0, 24)
};
struct imx_fracn_gppll_clk imx_fracn_gppll = {
@ -111,6 +113,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = {
PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
};
struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {

52
drivers/clk/imx/clk-imx93.c
View file

@ -13,6 +13,11 @@
#include "clk.h"
#define IMX93_CLK_END 207
#define PLAT_IMX93 BIT(0)
#define PLAT_IMX91 BIT(1)
enum clk_sel {
LOW_SPEED_IO_SEL,
NON_IO_SEL,
@ -50,6 +55,7 @@ static const struct imx93_clk_root {
u32 off;
enum clk_sel sel;
unsigned long flags;
unsigned long plat;
} root_array[] = {
/* a55/m33/bus critical clk for system run */
{ IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
@ -60,7 +66,7 @@ static const struct imx93_clk_root {
{ IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
{ IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
@ -117,15 +123,15 @@ static const struct imx93_clk_root {
{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
{ IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
{ IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, },
{ IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, },
{ IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, },
{ IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, },
{ IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, },
{ IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, },
{ IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, },
{ IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, },
{ IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, },
@ -134,13 +140,16 @@ static const struct imx93_clk_root {
{ IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, },
{ IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, },
{ IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, },
{ IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, },
{ IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, },
{ IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX91_CLK_ENET1_QOS_TSN, "enet1_qos_tsn_root", 0x2b00, NON_IO_SEL, 0, PLAT_IMX91, },
{ IMX91_CLK_ENET_TIMER, "enet_timer_root", 0x2b80, LOW_SPEED_IO_SEL, 0, PLAT_IMX91, },
{ IMX91_CLK_ENET2_REGULAR, "enet2_regular_root", 0x2c80, NON_IO_SEL, 0, PLAT_IMX91, },
{ IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
{ IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, },
{ IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, }
};
@ -152,6 +161,7 @@ static const struct imx93_clk_ccgr {
u32 off;
unsigned long flags;
u32 *shared_count;
unsigned long plat;
} ccgr_array[] = {
{ IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, },
/* M33 critical clk for system run */
@ -226,7 +236,7 @@ static const struct imx93_clk_ccgr {
{ IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3},
{ IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, },
{ IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, },
{ IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, },
{ IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, 0, NULL, PLAT_IMX93, },
{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
@ -240,8 +250,10 @@ static const struct imx93_clk_ccgr {
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-24m", 0x9dc0, },
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, },
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, },
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, },
{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, },
{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, },
/* Critical because clk accessed during CPU idle */
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, CLK_IS_CRITICAL},
{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
@ -257,6 +269,7 @@ static int imx93_clk_probe(struct udevice *dev)
struct clk osc_24m_clk, osc_32k_clk, ext1_clk;
void __iomem *base, *anatop_base;
int i, ret;
const unsigned long plat = (unsigned long)dev_get_driver_data(dev);
clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL));
@ -307,6 +320,8 @@ static int imx93_clk_probe(struct udevice *dev)
for (i = 0; i < ARRAY_SIZE(root_array); i++) {
root = &root_array[i];
if (root->plat && !(root->plat & plat))
continue;
clk_dm(root->clk, imx93_clk_composite_flags(root->name,
parent_names[root->sel],
4, base + root->off, 3,
@ -315,6 +330,8 @@ static int imx93_clk_probe(struct udevice *dev)
for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) {
ccgr = &ccgr_array[i];
if (ccgr->plat && !(ccgr->plat & plat))
continue;
clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name,
ccgr->flags, base + ccgr->off, 0, 1, 1, 3,
ccgr->shared_count));
@ -328,7 +345,8 @@ static int imx93_clk_probe(struct udevice *dev)
}
static const struct udevice_id imx93_clk_ids[] = {
{ .compatible = "fsl,imx93-ccm" },
{ .compatible = "fsl,imx93-ccm", .data = (unsigned long)PLAT_IMX93 },
{ .compatible = "fsl,imx91-ccm", .data = (unsigned long)PLAT_IMX91 },
{ /* Sentinel */ },
};

10
drivers/cpu/imx8_cpu.c
View file

@ -65,6 +65,14 @@ static const char *get_imx_type_str(u32 imxtype)
return "93(02)";/* iMX93 900Mhz Low performance Dual core without NPU */
case MXC_CPU_IMX9301:
return "93(01)";/* iMX93 900Mhz Low performance Single core without NPU */
case MXC_CPU_IMX91:
return "91(31)";/* iMX91 11x11 Full feature */
case MXC_CPU_IMX9121:
return "91(21)";/* iMX91 11x11 Low drive mode */
case MXC_CPU_IMX9111:
return "91(11)";/* iMX91 9x9 Reduced feature */
case MXC_CPU_IMX9101:
return "91(01)";/* iMX91 9x9 Specific feature */
default:
return "??";
}
@ -127,6 +135,8 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat)
if (IS_ENABLED(CONFIG_IMX8)) {
if (plat->cpu_rsrc == SC_R_A72)
idx = 2; /* use "cpu-thermal1" device */
} else if (IS_ENABLED(CONFIG_IMX91)) {
idx = 0;
} else {
idx = 1;
}

8
drivers/ddr/imx/phy/ddrphy_utils.c
View file

@ -144,6 +144,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(400));
dram_disable_bypass();
break;
case 1200:
dram_pll_init(MHZ(300));
dram_disable_bypass();
break;
case 1066:
dram_pll_init(MHZ(266));
dram_disable_bypass();
@ -152,6 +156,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(233));
dram_disable_bypass();
break;
case 800:
dram_pll_init(MHZ(200));
dram_disable_bypass();
break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();

2
drivers/gpio/imx_rgpio2p.c
View file

@ -231,7 +231,7 @@ static struct imx_rgpio2p_soc_data imx7ulp_data = {
.have_dual_base = true,
};
static struct imx_rgpio2p_soc_data imx8ulp_data = {
static struct imx_rgpio2p_soc_data imx8ulp_data __section(".data") = {
.have_dual_base = false,
};

1
drivers/pinctrl/nxp/pinctrl-imx93.c
View file

@ -22,6 +22,7 @@ static int imx93_pinctrl_probe(struct udevice *dev)
static const struct udevice_id imx93_pinctrl_match[] = {
{ .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
{ .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
{ /* sentinel */ }
};

6
dts/upstream/include/dt-bindings/clock/imx93-clock.h
View file

@ -204,6 +204,10 @@
#define IMX93_CLK_A55_SEL 199
#define IMX93_CLK_A55_CORE 200
#define IMX93_CLK_PDM_IPG 201
#define IMX93_CLK_END 202
#define IMX91_CLK_ENET1_QOS_TSN 202
#define IMX91_CLK_ENET_TIMER 203
#define IMX91_CLK_ENET2_REGULAR 204
#define IMX91_CLK_ENET2_REGULAR_GATE 205
#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
#endif

875
dts/upstream/src/arm64/freescale/imx91-11x11-evk.dts Normal file
View file

@ -0,0 +1,875 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
compatible = "fsl,imx91-11x11-evk", "fsl,imx91";
model = "NXP i.MX91 11X11 EVK board";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
rtc0 = &bbnsm_rtc;
};
chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "vref_1v8";
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "audio-pwr";
gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "WLAN_EN";
gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* IW612 wifi chip needs more delay than other wifi chips to complete
* the host interface initialization after power up, otherwise the
* internal state of IW612 may be unstable, resulting in the failure of
* the SDIO3.0 switch voltage.
*/
startup-delay-us = <20000>;
};
reg_vdd_12v: regulator-vdd-12v {
compatible = "regulator-fixed";
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "reg_vdd_12v";
gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vrpi_3v3: regulator-vrpi-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VRPI_3V3";
vin-supply = <&buck4>;
gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vrpi_5v: regulator-vrpi-5v {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "VRPI_5V";
gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x40000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
eee-broken-1000t;
};
};
};
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
pinctrl-names = "default", "sleep";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
};
};
};
/*
* When add, delete or change any target device setting in &lpi2c1,
* please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts.
*/
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-names = "default";
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
DCVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
lsm6dsm@6a {
compatible = "st,lsm6dso";
reg = <0x6a>;
};
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gpio3>;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2237500>;
regulator-min-microvolt = <650000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK4";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK5";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK6";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
regulator-name = "LDO1";
};
ldo4: LDO4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
regulator-name = "LDO4";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
#gpio-cells = <2>;
gpio-controller;
#pwm-cells = <3>;
gpio-reserved-ranges = <5 1>;
exp-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-names = "default";
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
status = "okay";
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x51>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
status = "okay";
typec2_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
status = "okay";
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&lpuart5 {
pinctrl-0 = <&pinctrl_uart5>;
pinctrl-names = "default";
status = "okay";
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX91_PAD_GPIO_IO25__CAN2_TX 0x139e
MX91_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_flexcan2_sleep: flexcan2sleepgrp {
fsl,pins = <
MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e
MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
>;
};
pinctrl_lcdif_gpio: lcdifgpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e
MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e
MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e
MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e
MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e
MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e
MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e
MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e
MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e
MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e
MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e
MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e
MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e
MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e
MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e
MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e
MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e
MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e
MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e
MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e
MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e
MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e
MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e
MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e
MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e
MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX91_PAD_PDM_CLK__PDM_CLK 0x31e
MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e
MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e
>;
};
pinctrl_pdm_sleep: pdmsleepgrp {
fsl,pins = <
MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e
MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e
MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
>;
};
pinctrl_sai1_sleep: sai1sleepgrp {
fsl,pins = <
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e
MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e
MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e
>;
};
pinctrl_sai3_sleep: sai3sleepgrp {
fsl,pins = <
MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e
MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e
MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e
MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e
MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e
MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e
>;
};
pinctrl_spdif_sleep: spdifsleepgrp {
fsl,pins = <
MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e
MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_sleep: usdhc3sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_wlan: usdhc3wlangrp {
fsl,pins = <
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
};

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dts/upstream/src/arm64/freescale/imx91-pinfunc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright 2024 NXP
*/
#ifndef __DTS_IMX91_PINFUNC_H
#define __DTS_IMX91_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00
#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00
#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00
#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00
#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00
#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00
#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00
#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00
#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00
#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00
#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00
#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00
#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01
#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00
#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00
#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00
#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00
#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01
#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00
#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00
#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00
#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00
#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01
#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00
#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00
#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00
#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00
#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00
#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00
#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01
#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00
#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00
#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01
#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00
#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00
#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00
#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00
#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00
#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00
#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00
#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00
#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01
#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00
#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00
#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01
#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00
#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00
#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00
#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00
#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00
#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00
#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00
#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00
#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01
#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00
#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00
#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01
#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00
#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00
#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00
#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00
#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00
#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00
#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00
#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00
#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00
#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01
#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00
#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00
#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00
#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00
#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00
#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00
#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00
#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00
#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01
#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01
#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00
#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01
#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00
#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01
#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00
#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00
#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01
#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00
#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00
#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01
#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00
#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00
#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00
#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00
#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01
#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00
#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00
#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01
#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01
#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00
#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00
#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01
#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01
#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00
#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01
#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00
#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01
#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00
#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00
#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01
#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00
#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00
#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00
#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00
#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00
#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00
#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00
#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00
#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00
#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00
#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00
#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD3__GPIO4_IO3 0x00a0 0x0250 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00
#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02
#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00
#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00
#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00
#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01
#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00
#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00
#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00
#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00
#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00
#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00
#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00
#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01
#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01
#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00
#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00
#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00
#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00
#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00
#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00
#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00
#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00
#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01
#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00
#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00
#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00
#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00
#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01
#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01
#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01
#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01
#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01
#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01
#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01
#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01
#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00
#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01
#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01
#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01
#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01
#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01
#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01
#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01
#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00
#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00
#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01
#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02
#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00
#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00
#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01
#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00
#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00
#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01
#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00
#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01
#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00
#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01
#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01
#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01
#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01
#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00
#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01
#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00
#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00
#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00
#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01
#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00
#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01
#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00
#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01
#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00
#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01
#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00
#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01
#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00
#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00
#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00
#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01
#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00
#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00
#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00
#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01
#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00
#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00
#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00
#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01
#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00
#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00
#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01
#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00
#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01
#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00
#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00
#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00
#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01
#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00
#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01
#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01
#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00
#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01
#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01
#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01
#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01
#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01
#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01
#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01
#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00
#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00
#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00
#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01
#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01
#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00
#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01
#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00
#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00
#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00
#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01
#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01
#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00
#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00
#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01
#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00
#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00
#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00
#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00
#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01
#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00
#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01
#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00
#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03
#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01
#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00
#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01
#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00
#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01
#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01
#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00
#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00
#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00
#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01
#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01
#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00
#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00
#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02
#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00
#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00
#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00
#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00
#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02
#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00
#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00
#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00
#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00
#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01
#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00
#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00
#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00
#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00
#define MX91_PAD_I2C2_SCL__GPIO1_IO3 0x0178 0x0328 0x0000 0x05 0x00
#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00
#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01
#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00
#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00
#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00
#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00
#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01
#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00
#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02
#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00
#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00
#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01
#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00
#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02
#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00
#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00
#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01
#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01
#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02
#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00
#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00
#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00
#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01
#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00
#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02
#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00
#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00
#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02
#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00
#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00
#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00
#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00
#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00
#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02
#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00
#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01
#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00
#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00
#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00
#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01
#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02
#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01
#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00
#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00
#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00
#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01
#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00
#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01
#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00
#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01
#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01
#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02
#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00
#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01
#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00
#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01
#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00
#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02
#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01
#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00
#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00
#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00
#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00
#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00
#endif /* __DTS_IMX91_PINFUNC_H */

70
dts/upstream/src/arm64/freescale/imx91.dtsi Normal file
View file

@ -0,0 +1,70 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx91-pinfunc.h"
#include "imx93.dtsi"
/delete-node/ &A55_1;
/delete-node/ &cm33;
/delete-node/ &mlmix;
/delete-node/ &mu1;
/delete-node/ &mu2;
&clk {
compatible = "fsl,imx91-ccm";
};
&eqos {
clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
};
&fec {
clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>,
<&clk IMX93_CLK_DUMMY>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&i3c1 {
clocks = <&clk IMX93_CLK_BUS_AON>,
<&clk IMX93_CLK_I3C1_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&i3c2 {
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_I3C2_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&iomuxc {
compatible = "fsl,imx91-iomuxc";
};
&tmu {
status = "disabled";
};
&{/soc@0/ddr-pmu@4e300dc0} {
compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
};
&{/thermal-zones/cpu-thermal/cooling-maps/map0} {
cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};

21
include/configs/imx91_evk.h Normal file
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@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2024 NXP
*/
#ifndef __IMX91_EVK_H
#define __IMX91_EVK_H
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#endif

46
include/configs/phycore_imx8mm.h
View file

@ -20,52 +20,6 @@
/* For RAW image gives a error info not panic */
#endif
#define CFG_EXTRA_ENV_SETTINGS \
"image=Image\0" \
"console=ttymxc2,115200\0" \
"fdt_addr=0x48000000\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \
"update_offset=0x42\0" \
"update_filename=flash.bin\0" \
"update_bootimg=" \
"mmc dev ${mmcdev} ; " \
"if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
"fi\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0 " \
"nfsroot=/nfs\0" \
"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
"nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0" \
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000

27
lib/hashtable.c
View file

@ -221,11 +221,32 @@ static int
do_callback(const struct env_entry *e, const char *name, const char *value,
enum env_op op, int flags)
{
int ret = 0;
#ifndef CONFIG_XPL_BUILD
if (e->callback)
return e->callback(name, value, op, flags);
static bool in_callback;
if (!e->callback || in_callback)
return 0;
/*
* In case there are two variables which each implement env callback
* that performs env_set() on the other variable, the callbacks will
* call each other recursively until the stack runs out. Prevent such
* a recursion from happening.
*
* Example which triggers this behavior:
* static int on_foo(...) { env_set("bar", 0); ... }
* static int on_bar(...) { env_set("foo", 0); ... }
* U_BOOT_ENV_CALLBACK(foo, on_foo);
* U_BOOT_ENV_CALLBACK(bar, on_bar);
*/
in_callback = true;
ret = e->callback(name, value, op, flags);
in_callback = false;
#endif
return 0;
return ret;
}
/*