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arm: dts: add ethernet related node for MT7629 SoC

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This patch adds ethernet gmac node for MT7629 with internal gigabit phy.

Signed-off-by: Mark Lee <Mark-MC.Lee@mediatek.com>
This commit is contained in:
Weijie Gao 2018-12-20 16:12:55 +08:00 • committed by Tom Rini
parent d9506a6fdd
commit 9d42b613a8
2 changed files with 54 additions and 0 deletions
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11
arch/arm/dts/mt7629-rfb.dts
View file

@ -22,6 +22,17 @@
}; };
}; };
&eth {
status = "okay";
mediatek,gmac-id = <1>;
phy-mode = "gmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pinctrl { &pinctrl {
qspi_pins: qspi-pins { qspi_pins: qspi-pins {
mux { mux {

43
arch/arm/dts/mt7629.dtsi
View file

@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt7629-power.h> #include <dt-bindings/power/mt7629-power.h>
#include <dt-bindings/reset/mtk-reset.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
/ { / {
@ -228,6 +229,48 @@
compatible = "mediatek,mt7629-ethsys", "syscon"; compatible = "mediatek,mt7629-ethsys", "syscon";
reg = <0x1b000000 0x1000>; reg = <0x1b000000 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7629-eth", "syscon";
reg = <0x1b100000 0x20000>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&topckgen CLK_TOP_F10M_REF_SEL>,
<&ethsys CLK_ETH_ESW_EN>,
<&ethsys CLK_ETH_GP0_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_FE_EN>,
<&sgmiisys0 CLK_SGMII_TX_EN>,
<&sgmiisys0 CLK_SGMII_RX_EN>,
<&sgmiisys0 CLK_SGMII_CDR_REF>,
<&sgmiisys0 CLK_SGMII_CDR_FB>,
<&sgmiisys1 CLK_SGMII_TX_EN>,
<&sgmiisys1 CLK_SGMII_RX_EN>,
<&sgmiisys1 CLK_SGMII_CDR_REF>,
<&sgmiisys1 CLK_SGMII_CDR_FB>,
<&apmixedsys CLK_APMIXED_SGMIPLL>,
<&apmixedsys CLK_APMIXED_ETH2PLL>;
clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
"fe", "sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
"sgmii2_tx250m", "sgmii2_rx250m",
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "eth2pll";
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&topckgen CLK_TOP_F10M_REF_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
<&topckgen CLK_TOP_SGMIIPLL_D2>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
resets = <&ethsys ETHSYS_FE_RST>;
reset-names = "fe";
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>;
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
}; };
sgmiisys0: syscon@1b128000 { sgmiisys0: syscon@1b128000 {