dt-bindings: sunxi: Update clock/reset binding headers

Some devicetree updates make use of newly-exposed clocks and resets.
To support that, copy the binding headers from the Linux v5.18-rc1 tag.

Signed-off-by: Samuel Holland <samuel@sholland.org>
This commit is contained in:
Samuel Holland 2022-04-27 15:31:20 -05:00 committed by Andre Przywara
parent 6f00b97d7e
commit 9a50489c60
8 changed files with 16 additions and 23 deletions

View file

@ -113,7 +113,7 @@
#define CLK_USB_OHCI0 91
#define CLK_USB_OHCI1 93
#define CLK_DRAM 94
#define CLK_DRAM_VE 95
#define CLK_DRAM_CSI 96
#define CLK_DRAM_DEINTERLACE 97

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@ -1,17 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_SUN5I_H_
@ -100,7 +91,7 @@
#define CLK_AVS 96
#define CLK_HDMI 97
#define CLK_GPU 98
#define CLK_MBUS 99
#define CLK_IEP 100
#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */

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@ -49,6 +49,8 @@
#define CLK_PLL_VIDEO1_2X 13
#define CLK_PLL_MIPI 15
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23

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@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define CLK_PLL_MIPI 13
#define CLK_CPUX 18
#define CLK_BUS_MIPI_DSI 23

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@ -126,7 +126,7 @@
#define CLK_USB_OHCI1 93
#define CLK_USB_OHCI2 94
#define CLK_USB_OHCI3 95
#define CLK_DRAM 96
#define CLK_DRAM_VE 97
#define CLK_DRAM_CSI 98
#define CLK_DRAM_DEINTERLACE 99

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@ -104,4 +104,8 @@
#define CLK_MIPI_CSI 73
/* Clocks not available on V3s */
#define CLK_BUS_I2S0 75
#define CLK_I2S0 76
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */

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@ -1,17 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _RST_SUN5I_H_

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@ -75,4 +75,7 @@
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
/* Reset lines not available on V3s */
#define RST_BUS_I2S0 52
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */