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net: emaclite: Convert MDIO to use register offset
Use u-boot coding style how to setup and access MDIO bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Michal Simek
parent
d722e8641b
commit
9a23c49662
1 changed files with 56 additions and 36 deletions
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@ -50,12 +50,6 @@
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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/* MDIO */
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#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
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#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
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#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
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#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
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/* MDIO Address Register Bit Masks */
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#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
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#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
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@ -72,12 +66,36 @@
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#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
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#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
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struct emaclite_regs {
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u32 tx_ping; /* 0x0 - TX Ping buffer */
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u32 reserved1[504];
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u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
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u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
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u32 mdiord;/* 0x7ec - MDIO Read Data Register */
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u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
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u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
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u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
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u32 tx_ping_tsr; /* 0x7fc - Tx status */
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u32 tx_pong; /* 0x800 - TX Pong buffer */
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u32 reserved2[508];
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u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
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u32 reserved3; /* 0xff8 */
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u32 tx_pong_tsr; /* 0xffc - Tx status */
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u32 rx_ping; /* 0x1000 - Receive Buffer */
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u32 reserved4[510];
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u32 rx_ping_rsr; /* 0x17fc - Rx status */
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u32 rx_pong; /* 0x1800 - Receive Buffer */
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u32 reserved5[510];
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u32 rx_pong_rsr; /* 0x1ffc - Rx status */
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};
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struct xemaclite {
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u32 nexttxbuffertouse; /* Next TX buffer to write to */
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u32 nextrxbuffertouse; /* Next RX buffer to read from */
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u32 txpp; /* TX ping pong buffer */
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u32 rxpp; /* RX ping pong buffer */
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int phyaddr;
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struct emaclite_regs *regs;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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@ -169,38 +187,39 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
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return -ETIMEDOUT;
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}
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static int mdio_wait(struct eth_device *dev)
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static int mdio_wait(struct emaclite_regs *regs)
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{
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return wait_for_bit(__func__,
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(u32 *)(dev->iobase + XEL_MDIOCTRL_OFFSET),
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return wait_for_bit(__func__, ®s->mdioctrl,
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XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
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}
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static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
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static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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u16 *data)
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{
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if (mdio_wait(dev))
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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return 1;
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u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET);
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out_be32(dev->iobase + XEL_MDIOADDR_OFFSET,
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XEL_MDIOADDR_OP_MASK |
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u32 ctrl_reg = in_be32(®s->mdioctrl);
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out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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if (mdio_wait(dev))
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if (mdio_wait(regs))
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return 1;
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/* Read data */
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*data = in_be32(dev->iobase + XEL_MDIORD_OFFSET);
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*data = in_be32(®s->mdiord);
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return 0;
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}
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static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
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static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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u16 data)
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{
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if (mdio_wait(dev))
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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return 1;
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/*
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@ -209,15 +228,13 @@ static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
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* Data register. Finally, set the Status bit in the MDIO Control
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* register to start a MDIO write transaction.
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*/
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u32 ctrl_reg = in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET);
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out_be32(dev->iobase + XEL_MDIOADDR_OFFSET,
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~XEL_MDIOADDR_OP_MASK &
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u32 ctrl_reg = in_be32(®s->mdioctrl);
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out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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out_be32(dev->iobase + XEL_MDIOWR_OFFSET, data);
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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out_be32(®s->mdiowr, data);
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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if (mdio_wait(dev))
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if (mdio_wait(regs))
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return 1;
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return 0;
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@ -254,7 +271,7 @@ static int setup_phy(struct eth_device *dev)
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SUPPORTED_100baseT_Full;
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if (emaclite->phyaddr != -1) {
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phyread(dev, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
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phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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@ -270,7 +287,7 @@ static int setup_phy(struct eth_device *dev)
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if (emaclite->phyaddr == -1) {
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/* detect the PHY address */
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for (i = 31; i >= 0; i--) {
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phyread(dev, i, PHY_DETECT_REG, &phyreg);
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phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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@ -310,6 +327,8 @@ static int setup_phy(struct eth_device *dev)
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static int emaclite_init(struct eth_device *dev, bd_t *bis)
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{
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struct xemaclite *emaclite = dev->priv;
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struct emaclite_regs *regs = emaclite->regs;
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debug("EmacLite Initialization Started\n");
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/*
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@ -352,9 +371,8 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis)
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XEL_RSR_RECV_IE_MASK);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET, XEL_MDIOCTRL_MDIOEN_MASK);
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if (in_be32(dev->iobase + XEL_MDIOCTRL_OFFSET) &
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XEL_MDIOCTRL_MDIOEN_MASK)
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out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
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if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
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if (!setup_phy(dev))
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return -1;
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#endif
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@ -536,7 +554,7 @@ static int emaclite_miiphy_read(const char *devname, uchar addr,
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u32 ret;
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struct eth_device *dev = eth_get_dev();
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ret = phyread(dev, addr, reg, val);
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ret = phyread(dev->priv, addr, reg, val);
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debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
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return ret;
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}
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@ -547,7 +565,7 @@ static int emaclite_miiphy_write(const char *devname, uchar addr,
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struct eth_device *dev = eth_get_dev();
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debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
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return phywrite(dev, addr, reg, val);
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return phywrite(dev->priv, addr, reg, val);
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}
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#endif
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@ -556,6 +574,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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{
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struct eth_device *dev;
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struct xemaclite *emaclite;
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struct emaclite_regs *regs;
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dev = calloc(1, sizeof(*dev));
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if (dev == NULL)
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@ -574,6 +593,8 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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sprintf(dev->name, "Xelite.%lx", base_addr);
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emaclite->regs = (struct emaclite_regs *)base_addr;
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regs = emaclite->regs;
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dev->iobase = base_addr;
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dev->init = emaclite_init;
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dev->halt = emaclite_halt;
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@ -592,8 +613,7 @@ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
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miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
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emaclite->bus = miiphy_get_dev_by_name(dev->name);
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out_be32(dev->iobase + XEL_MDIOCTRL_OFFSET,
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XEL_MDIOCTRL_MDIOEN_MASK);
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out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
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#endif
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return 1;
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