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clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching

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Do not cache the single CPG MODE register bit 12, instead cache the
entire register value, and only pick the matching bit from the cached
value when core clock of type MDSEL or PE are used. Both MDSEL and PE
clock type currently define .offset field as 12 on Gen3, which means
this code will use bit 12 on Gen3 again, however there are additional
clock on Gen4 which use different bits, and having this flexibility
in place now will be useful when adding Gen4.

No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-02-28 07:25:11 +01:00
parent f54eb0bad6
commit 99c7e03119
2 changed files with 10 additions and 10 deletions
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18
drivers/clk/renesas/clk-rcar-gen3.c
View file

@ -55,6 +55,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
struct cpg_mssr_info *info, struct clk *parent)
{
const struct cpg_core_clk *core;
u8 shift;
int ret;
if (!renesas_clk_is_mod(clk)) {
@ -63,8 +64,9 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
return ret;
if (core->type == CLK_TYPE_GEN3_MDSEL) {
shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
parent->dev = clk->dev;
parent->id = core->parent >> (priv->sscg ? 16 : 0);
parent->id = core->parent >> shift;
parent->id &= 0xffff;
return 0;
}
@ -183,6 +185,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
priv->cpg_pll_config;
u32 value, div;
u64 rate = 0;
u8 shift;
int ret;
debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
@ -277,11 +280,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
"FIXED");
case CLK_TYPE_GEN3_MDSEL:
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
div = (core->div >> shift) & 0xffff;
rate = gen3_clk_get_rate64(&parent) / div;
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
__func__, __LINE__,
(core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
__func__, __LINE__, (core->parent >> shift) & 0xffff,
div, rate);
return rate;
@ -407,7 +410,6 @@ static int gen3_clk_probe(struct udevice *dev)
struct cpg_mssr_info *info =
(struct cpg_mssr_info *)dev_get_driver_data(dev);
fdt_addr_t rst_base;
u32 cpg_mode;
int ret;
priv->base = dev_read_addr_ptr(dev);
@ -423,15 +425,13 @@ static int gen3_clk_probe(struct udevice *dev)
if (rst_base == FDT_ADDR_T_NONE)
return -EINVAL;
cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
if (!priv->cpg_pll_config->extal_div)
return -EINVAL;
priv->sscg = !(cpg_mode & BIT(12));
if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
priv->info->status_regs = mstpsr;
priv->info->control_regs = smstpcr;

2
drivers/clk/renesas/rcar-gen3-cpg.h
View file

@ -132,7 +132,7 @@ struct gen3_clk_priv {
struct cpg_mssr_info *info;
struct clk clk_extal;
struct clk clk_extalr;
bool sscg;
u32 cpg_mode;
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
};