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ddr: imx: Add i.MX9 DDR controller driver
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
Stefano Babic
parent
e631185a20
commit
99c7cc58e1
16 changed files with 1077 additions and 25 deletions
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@ -11,6 +11,11 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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static unsigned int g_cdd_rr_max[4];
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static unsigned int g_cdd_rw_max[4];
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static unsigned int g_cdd_wr_max[4];
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static unsigned int g_cdd_ww_max[4];
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void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
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{
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int i = 0;
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@ -91,6 +96,215 @@ void __weak board_dram_ecc_scrub(void)
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{
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}
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void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
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unsigned int mr_data)
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{
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unsigned int tmp;
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/*
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* 1. Poll MRSTAT.mr_wr_busy until it is 0.
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* This checks that there is no outstanding MR transaction.
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* No writes should be performed to MRCTRL0 and MRCTRL1 if
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* MRSTAT.mr_wr_busy = 1.
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*/
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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/*
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* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
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* (for MRWs) MRCTRL1.mr_data to define the MR transaction.
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*/
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
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reg32setbit(DDRC_MRCTRL0(0), 31);
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}
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unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
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{
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unsigned int tmp;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
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reg32setbit(DDRC_MRCTRL0(0), 31);
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do {
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tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
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} while ((tmp & 0x8) == 0);
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tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
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tmp = tmp & 0xff;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
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return tmp;
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}
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static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
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unsigned int addr_end)
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{
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unsigned int i, imax = 0;
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for (i = addr_start; i <= addr_end; i++) {
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if (((data[i] >> 7) == 0) && data[i] > imax)
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imax = data[i];
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}
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return imax;
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}
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void get_trained_CDD(u32 fsp)
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{
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unsigned int i, ddr_type, tmp;
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unsigned int cdd_cha[12], cdd_chb[12];
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unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
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unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
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ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
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if (ddr_type == 0x20) {
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for (i = 0; i < 6; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
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cdd_cha[i * 2] = tmp & 0xff;
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cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
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}
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for (i = 0; i < 7; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
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if (i == 0) {
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cdd_cha[0] = (tmp >> 8) & 0xff;
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} else if (i == 6) {
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cdd_cha[11] = tmp & 0xff;
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} else {
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cdd_chb[i * 2 - 1] = tmp & 0xff;
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cdd_chb[i * 2] = (tmp >> 8) & 0xff;
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}
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}
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cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
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cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
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cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
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cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
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cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
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cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
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cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
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cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
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g_cdd_rr_max[fsp] =
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cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
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g_cdd_rw_max[fsp] =
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cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
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g_cdd_wr_max[fsp] =
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cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
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g_cdd_ww_max[fsp] =
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cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
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} else {
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unsigned int ddr4_cdd[64];
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for (i = 0; i < 29; i++) {
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tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
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ddr4_cdd[i * 2] = tmp & 0xff;
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ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
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}
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g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
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g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
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g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
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g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
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}
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}
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void update_umctl2_rank_space_setting(unsigned int pstat_num)
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{
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unsigned int i, ddr_type;
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unsigned int addr_slot, rdata, tmp, tmp_t;
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unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
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ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
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for (i = 0; i < pstat_num; i++) {
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addr_slot = i ? (i + 1) * 0x1000 : 0;
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if (ddr_type == 0x20) {
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/* update r2w:[13:8], w2r:[5:0] */
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rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
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ddrc_w2r = rdata & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
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else
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
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ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
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ddrc_r2w = (rdata >> 8) & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
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else
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
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ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
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reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
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} else {
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/* update w2r:[5:0] */
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rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
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ddrc_w2r = rdata & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
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else
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tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
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ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
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reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
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/* update r2w:[13:8] */
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rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
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ddrc_r2w = (rdata >> 8) & 0x3f;
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if (is_imx8mp())
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
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else
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tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
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ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
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tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
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reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
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}
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if (!is_imx8mq()) {
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/*
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* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static)
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*/
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rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
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ddrc_wr_gap = (rdata >> 8) & 0xf;
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if (is_imx8mp())
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tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
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else
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tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
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ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
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ddrc_rd_gap = (rdata >> 4) & 0xf;
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if (is_imx8mp())
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tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
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else
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tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
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ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
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tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
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reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
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}
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}
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if (is_imx8mq()) {
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/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
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rdata = reg32_read(DDRC_RANKCTL(0));
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ddrc_wr_gap = (rdata >> 8) & 0xf;
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tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
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ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
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ddrc_rd_gap = (rdata >> 4) & 0xf;
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tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
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ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
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tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
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reg32_write(DDRC_RANKCTL(0), tmp_t);
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}
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}
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int ddr_init(struct dram_timing_info *dram_timing)
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{
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unsigned int tmp, initial_drate, target_freq;
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@ -250,3 +464,8 @@ int ddr_init(struct dram_timing_info *dram_timing)
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return 0;
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}
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ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
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{
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return 4 * paddr_apb_from_ctlr;
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}
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