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clk: mediatek: mt7988: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel linux. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Tested-by: Frank Wunderlich <frank-w@public-files.de>
This commit is contained in:
Christian Marangi
Tom Rini
parent
ef4a648587
commit
99c5fa184b
3 changed files with 651 additions and 651 deletions
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@ -255,11 +255,11 @@
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compatible = "mediatek,hsuart";
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reg = <0 0x11000000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_52M_UART0_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg CK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
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<&topckgen CK_TOP_UART_SEL>;
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clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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@ -267,11 +267,11 @@
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compatible = "mediatek,hsuart";
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reg = <0 0x11000100 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_52M_UART1_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg CK_INFRA_MUX_UART1_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
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<&topckgen CK_TOP_UART_SEL>;
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clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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@ -279,11 +279,11 @@
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compatible = "mediatek,hsuart";
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reg = <0 0x11000200 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_52M_UART2_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg CK_INFRA_MUX_UART2_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_XTAL>,
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<&topckgen CK_TOP_UART_SEL>;
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clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART2_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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@ -294,8 +294,8 @@
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CK_INFRA_I2C_BCK>,
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<&infracfg CK_INFRA_66M_AP_DMA_BCK>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -309,8 +309,8 @@
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<0 0x10217100 0 0x80>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CK_INFRA_I2C_BCK>,
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<&infracfg CK_INFRA_66M_AP_DMA_BCK>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -324,8 +324,8 @@
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<0 0x10217180 0 0x80>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CK_INFRA_I2C_BCK>,
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<&infracfg CK_INFRA_66M_AP_DMA_BCK>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -336,16 +336,16 @@
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compatible = "mediatek,mt7988-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CK_INFRA_66M_PWM_BCK>,
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<&infracfg CK_INFRA_66M_PWM_HCK>,
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<&infracfg CK_INFRA_66M_PWM_CK1>,
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<&infracfg CK_INFRA_66M_PWM_CK2>,
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<&infracfg CK_INFRA_66M_PWM_CK3>,
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<&infracfg CK_INFRA_66M_PWM_CK4>,
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<&infracfg CK_INFRA_66M_PWM_CK5>,
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<&infracfg CK_INFRA_66M_PWM_CK6>,
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<&infracfg CK_INFRA_66M_PWM_CK7>,
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<&infracfg CK_INFRA_66M_PWM_CK8>;
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clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_CK1>,
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<&infracfg CLK_INFRA_66M_PWM_CK2>,
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<&infracfg CLK_INFRA_66M_PWM_CK3>,
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<&infracfg CLK_INFRA_66M_PWM_CK4>,
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<&infracfg CLK_INFRA_66M_PWM_CK5>,
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<&infracfg CLK_INFRA_66M_PWM_CK6>,
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<&infracfg CLK_INFRA_66M_PWM_CK7>,
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<&infracfg CLK_INFRA_66M_PWM_CK8>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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"pwm4","pwm5","pwm6","pwm7","pwm8";
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status = "disabled";
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@ -358,14 +358,14 @@
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<0 0x11002000 0 0x1000>;
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reg-names = "nfi", "ecc";
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_SPINFI>,
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<&infracfg CK_INFRA_NFI>,
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<&infracfg CK_INFRA_66M_NFI_HCK>;
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clocks = <&infracfg CLK_INFRA_SPINFI>,
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<&infracfg CLK_INFRA_NFI>,
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<&infracfg CLK_INFRA_66M_NFI_HCK>;
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clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
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<&topckgen CK_TOP_NFI1X_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_MPLL_D8>,
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<&topckgen CK_TOP_MPLL_D8>;
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assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
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<&topckgen CLK_TOP_NFI1X_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
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<&topckgen CLK_TOP_MPLL_D8>;
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status = "disabled";
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};
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@ -401,10 +401,10 @@
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"mediatek,mt7986-mmc";
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reg = <0 0x11230000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_MSDC400>,
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<&infracfg CK_INFRA_MSDC2_HCK>,
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<&infracfg CK_INFRA_133M_MSDC_0_HCK>,
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<&infracfg CK_INFRA_66M_MSDC_0_HCK>;
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clocks = <&infracfg CLK_INFRA_MSDC400>,
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<&infracfg CLK_INFRA_MSDC2_HCK>,
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<&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
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<&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
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clock-names = "source", "hclk", "source_cg", "axi_cg";
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status = "disabled";
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};
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File diff suppressed because it is too large
Load diff
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@ -10,255 +10,255 @@
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/* INFRACFG_AO */
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/* mtk_mux */
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#define CK_INFRA_MUX_UART0_SEL 0
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#define CK_INFRA_MUX_UART1_SEL 1
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#define CK_INFRA_MUX_UART2_SEL 2
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#define CK_INFRA_MUX_SPI0_SEL 3
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#define CK_INFRA_MUX_SPI1_SEL 4
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#define CK_INFRA_MUX_SPI2_SEL 5
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#define CK_INFRA_PWM_SEL 6
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#define CK_INFRA_PWM_CK1_SEL 7
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#define CK_INFRA_PWM_CK2_SEL 8
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#define CK_INFRA_PWM_CK3_SEL 9
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#define CK_INFRA_PWM_CK4_SEL 10
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#define CK_INFRA_PWM_CK5_SEL 11
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#define CK_INFRA_PWM_CK6_SEL 12
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#define CK_INFRA_PWM_CK7_SEL 13
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#define CK_INFRA_PWM_CK8_SEL 14
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#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
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#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
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#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
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#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
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#define CLK_INFRA_MUX_UART0_SEL 0
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#define CLK_INFRA_MUX_UART1_SEL 1
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#define CLK_INFRA_MUX_UART2_SEL 2
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#define CLK_INFRA_MUX_SPI0_SEL 3
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#define CLK_INFRA_MUX_SPI1_SEL 4
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#define CLK_INFRA_MUX_SPI2_SEL 5
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#define CLK_INFRA_PWM_SEL 6
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#define CLK_INFRA_PWM_CK1_SEL 7
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#define CLK_INFRA_PWM_CK2_SEL 8
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#define CLK_INFRA_PWM_CK3_SEL 9
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#define CLK_INFRA_PWM_CK4_SEL 10
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#define CLK_INFRA_PWM_CK5_SEL 11
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#define CLK_INFRA_PWM_CK6_SEL 12
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#define CLK_INFRA_PWM_CK7_SEL 13
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#define CLK_INFRA_PWM_CK8_SEL 14
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
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#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
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/* INFRACFG */
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/* mtk_gate */
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#define CK_INFRA_PCIE_PERI_26M_CK_P0 19
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#define CK_INFRA_PCIE_PERI_26M_CK_P1 20
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#define CK_INFRA_PCIE_PERI_26M_CK_P2 21
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#define CK_INFRA_PCIE_PERI_26M_CK_P3 22
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#define CK_INFRA_66M_GPT_BCK 23
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#define CK_INFRA_66M_PWM_HCK 24
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#define CK_INFRA_66M_PWM_BCK 25
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#define CK_INFRA_66M_PWM_CK1 26
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#define CK_INFRA_66M_PWM_CK2 27
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#define CK_INFRA_66M_PWM_CK3 28
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#define CK_INFRA_66M_PWM_CK4 29
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#define CK_INFRA_66M_PWM_CK5 30
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#define CK_INFRA_66M_PWM_CK6 31
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#define CK_INFRA_66M_PWM_CK7 32
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#define CK_INFRA_66M_PWM_CK8 33
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#define CK_INFRA_133M_CQDMA_BCK 34
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#define CK_INFRA_66M_AUD_SLV_BCK 35
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#define CK_INFRA_AUD_26M 36
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#define CK_INFRA_AUD_L 37
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#define CK_INFRA_AUD_AUD 38
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#define CK_INFRA_AUD_EG2 39
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#define CK_INFRA_DRAMC_F26M 40
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#define CK_INFRA_133M_DBG_ACKM 41
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#define CK_INFRA_66M_AP_DMA_BCK 42
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#define CK_INFRA_66M_SEJ_BCK 43
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#define CK_INFRA_PRE_CK_SEJ_F13M 44
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/* #define CK_INFRA_66M_TRNG 44 */
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#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
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#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
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#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
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#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
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#define CLK_INFRA_66M_GPT_BCK 23
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#define CLK_INFRA_66M_PWM_HCK 24
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#define CLK_INFRA_66M_PWM_BCK 25
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#define CLK_INFRA_66M_PWM_CK1 26
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#define CLK_INFRA_66M_PWM_CK2 27
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#define CLK_INFRA_66M_PWM_CK3 28
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#define CLK_INFRA_66M_PWM_CK4 29
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#define CLK_INFRA_66M_PWM_CK5 30
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#define CLK_INFRA_66M_PWM_CK6 31
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#define CLK_INFRA_66M_PWM_CK7 32
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#define CLK_INFRA_66M_PWM_CK8 33
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#define CLK_INFRA_133M_CQDMA_BCK 34
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#define CLK_INFRA_66M_AUD_SLV_BCK 35
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#define CLK_INFRA_AUD_26M 36
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#define CLK_INFRA_AUD_L 37
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#define CLK_INFRA_AUD_AUD 38
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#define CLK_INFRA_AUD_EG2 39
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#define CLK_INFRA_DRAMC_F26M 40
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#define CLK_INFRA_133M_DBG_ACKM 41
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#define CLK_INFRA_66M_AP_DMA_BCK 42
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#define CLK_INFRA_66M_SEJ_BCK 43
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#define CLK_INFRA_PRE_CK_SEJ_F13M 44
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/* #define CLK_INFRA_66M_TRNG 44 */
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#define CLK_INFRA_26M_THERM_SYSTEM 45
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#define CLK_INFRA_I2C_BCK 46
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/* #define CK_INFRA_66M_UART0_PCK 46 */
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/* #define CK_INFRA_66M_UART1_PCK 47 */
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/* #define CK_INFRA_66M_UART2_PCK 48 */
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#define CK_INFRA_52M_UART0_CK 47
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#define CK_INFRA_52M_UART1_CK 48
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#define CK_INFRA_52M_UART2_CK 49
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#define CK_INFRA_NFI 50
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#define CK_INFRA_SPINFI 51
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#define CK_INFRA_66M_NFI_HCK 52
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#define CK_INFRA_104M_SPI0 53
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#define CK_INFRA_104M_SPI1 54
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#define CK_INFRA_104M_SPI2_BCK 55
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#define CK_INFRA_66M_SPI0_HCK 56
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#define CK_INFRA_66M_SPI1_HCK 57
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#define CK_INFRA_66M_SPI2_HCK 58
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#define CK_INFRA_66M_FLASHIF_AXI 59
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#define CK_INFRA_RTC 60
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#define CK_INFRA_26M_ADC_BCK 61
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#define CK_INFRA_RC_ADC 62
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#define CK_INFRA_MSDC400 63
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#define CK_INFRA_MSDC2_HCK 64
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#define CK_INFRA_133M_MSDC_0_HCK 65
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#define CK_INFRA_66M_MSDC_0_HCK 66
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#define CK_INFRA_133M_CPUM_BCK 67
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#define CK_INFRA_BIST2FPC 68
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#define CK_INFRA_I2C_X16W_MCK_CK_P1 69
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#define CK_INFRA_I2C_X16W_PCK_CK_P1 70
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#define CK_INFRA_133M_USB_HCK 71
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#define CK_INFRA_133M_USB_HCK_CK_P1 72
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#define CK_INFRA_66M_USB_HCK 73
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#define CK_INFRA_66M_USB_HCK_CK_P1 74
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#define CK_INFRA_USB_SYS 75
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#define CK_INFRA_USB_SYS_CK_P1 76
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#define CK_INFRA_USB_REF 77
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#define CK_INFRA_USB_CK_P1 78
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#define CK_INFRA_USB_FRMCNT 79
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#define CK_INFRA_USB_FRMCNT_CK_P1 80
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#define CK_INFRA_USB_PIPE 81
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#define CK_INFRA_USB_PIPE_CK_P1 82
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#define CK_INFRA_USB_UTMI 83
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#define CK_INFRA_USB_UTMI_CK_P1 84
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#define CK_INFRA_USB_XHCI 85
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#define CK_INFRA_USB_XHCI_CK_P1 86
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#define CK_INFRA_PCIE_GFMUX_TL_P0 87
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#define CK_INFRA_PCIE_GFMUX_TL_P1 88
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#define CK_INFRA_PCIE_GFMUX_TL_P2 89
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#define CK_INFRA_PCIE_GFMUX_TL_P3 90
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#define CK_INFRA_PCIE_PIPE_P0 91
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#define CK_INFRA_PCIE_PIPE_P1 92
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#define CK_INFRA_PCIE_PIPE_P2 93
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#define CK_INFRA_PCIE_PIPE_P3 94
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#define CK_INFRA_133M_PCIE_CK_P0 95
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#define CK_INFRA_133M_PCIE_CK_P1 96
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#define CK_INFRA_133M_PCIE_CK_P2 97
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#define CK_INFRA_133M_PCIE_CK_P3 98
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/* #define CLK_INFRA_66M_UART0_PCK 46 */
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/* #define CLK_INFRA_66M_UART1_PCK 47 */
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/* #define CLK_INFRA_66M_UART2_PCK 48 */
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#define CLK_INFRA_52M_UART0_CK 47
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#define CLK_INFRA_52M_UART1_CK 48
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#define CLK_INFRA_52M_UART2_CK 49
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#define CLK_INFRA_NFI 50
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#define CLK_INFRA_SPINFI 51
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#define CLK_INFRA_66M_NFI_HCK 52
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#define CLK_INFRA_104M_SPI0 53
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#define CLK_INFRA_104M_SPI1 54
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#define CLK_INFRA_104M_SPI2_BCK 55
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#define CLK_INFRA_66M_SPI0_HCK 56
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#define CLK_INFRA_66M_SPI1_HCK 57
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#define CLK_INFRA_66M_SPI2_HCK 58
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#define CLK_INFRA_66M_FLASHIF_AXI 59
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#define CLK_INFRA_RTC 60
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#define CLK_INFRA_26M_ADC_BCK 61
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||||
#define CLK_INFRA_RC_ADC 62
|
||||
#define CLK_INFRA_MSDC400 63
|
||||
#define CLK_INFRA_MSDC2_HCK 64
|
||||
#define CLK_INFRA_133M_MSDC_0_HCK 65
|
||||
#define CLK_INFRA_66M_MSDC_0_HCK 66
|
||||
#define CLK_INFRA_133M_CPUM_BCK 67
|
||||
#define CLK_INFRA_BIST2FPC 68
|
||||
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
|
||||
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
|
||||
#define CLK_INFRA_133M_USB_HCK 71
|
||||
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
|
||||
#define CLK_INFRA_66M_USB_HCK 73
|
||||
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
|
||||
#define CLK_INFRA_USB_SYS 75
|
||||
#define CLK_INFRA_USB_SYS_CK_P1 76
|
||||
#define CLK_INFRA_USB_REF 77
|
||||
#define CLK_INFRA_USB_CK_P1 78
|
||||
#define CLK_INFRA_USB_FRMCNT 79
|
||||
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
|
||||
#define CLK_INFRA_USB_PIPE 81
|
||||
#define CLK_INFRA_USB_PIPE_CK_P1 82
|
||||
#define CLK_INFRA_USB_UTMI 83
|
||||
#define CLK_INFRA_USB_UTMI_CK_P1 84
|
||||
#define CLK_INFRA_USB_XHCI 85
|
||||
#define CLK_INFRA_USB_XHCI_CK_P1 86
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
|
||||
#define CLK_INFRA_PCIE_PIPE_P0 91
|
||||
#define CLK_INFRA_PCIE_PIPE_P1 92
|
||||
#define CLK_INFRA_PCIE_PIPE_P2 93
|
||||
#define CLK_INFRA_PCIE_PIPE_P3 94
|
||||
#define CLK_INFRA_133M_PCIE_CK_P0 95
|
||||
#define CLK_INFRA_133M_PCIE_CK_P1 96
|
||||
#define CLK_INFRA_133M_PCIE_CK_P2 97
|
||||
#define CLK_INFRA_133M_PCIE_CK_P3 98
|
||||
|
||||
/* TOPCKGEN */
|
||||
/* mtk_fixed_clk */
|
||||
#define CK_TOP_XTAL 0
|
||||
#define CLK_TOP_XTAL 0
|
||||
/* mtk_fixed_factor */
|
||||
#define CK_TOP_XTAL_D2 1
|
||||
#define CK_TOP_RTC_32K 2
|
||||
#define CK_TOP_RTC_32P7K 3
|
||||
#define CK_TOP_MPLL_D2 4
|
||||
#define CK_TOP_MPLL_D3_D2 5
|
||||
#define CK_TOP_MPLL_D4 6
|
||||
#define CK_TOP_MPLL_D8 7
|
||||
#define CK_TOP_MPLL_D8_D2 8
|
||||
#define CK_TOP_MMPLL_D2 9
|
||||
#define CK_TOP_MMPLL_D3_D5 10
|
||||
#define CK_TOP_MMPLL_D4 11
|
||||
#define CK_TOP_MMPLL_D6_D2 12
|
||||
#define CK_TOP_MMPLL_D8 13
|
||||
#define CK_TOP_APLL2_D4 14
|
||||
#define CK_TOP_NET1PLL_D4 15
|
||||
#define CK_TOP_NET1PLL_D5 16
|
||||
#define CK_TOP_NET1PLL_D5_D2 17
|
||||
#define CK_TOP_NET1PLL_D5_D4 18
|
||||
#define CK_TOP_NET1PLL_D8 19
|
||||
#define CK_TOP_NET1PLL_D8_D2 20
|
||||
#define CK_TOP_NET1PLL_D8_D4 21
|
||||
#define CK_TOP_NET1PLL_D8_D8 22
|
||||
#define CK_TOP_NET1PLL_D8_D16 23
|
||||
#define CK_TOP_NET2PLL_D2 24
|
||||
#define CK_TOP_NET2PLL_D4 25
|
||||
#define CK_TOP_NET2PLL_D4_D4 26
|
||||
#define CK_TOP_NET2PLL_D4_D8 27
|
||||
#define CK_TOP_NET2PLL_D6 28
|
||||
#define CK_TOP_NET2PLL_D8 29
|
||||
#define CLK_TOP_XTAL_D2 1
|
||||
#define CLK_TOP_RTC_32K 2
|
||||
#define CLK_TOP_RTC_32P7K 3
|
||||
#define CLK_TOP_MPLL_D2 4
|
||||
#define CLK_TOP_MPLL_D3_D2 5
|
||||
#define CLK_TOP_MPLL_D4 6
|
||||
#define CLK_TOP_MPLL_D8 7
|
||||
#define CLK_TOP_MPLL_D8_D2 8
|
||||
#define CLK_TOP_MMPLL_D2 9
|
||||
#define CLK_TOP_MMPLL_D3_D5 10
|
||||
#define CLK_TOP_MMPLL_D4 11
|
||||
#define CLK_TOP_MMPLL_D6_D2 12
|
||||
#define CLK_TOP_MMPLL_D8 13
|
||||
#define CLK_TOP_APLL2_D4 14
|
||||
#define CLK_TOP_NET1PLL_D4 15
|
||||
#define CLK_TOP_NET1PLL_D5 16
|
||||
#define CLK_TOP_NET1PLL_D5_D2 17
|
||||
#define CLK_TOP_NET1PLL_D5_D4 18
|
||||
#define CLK_TOP_NET1PLL_D8 19
|
||||
#define CLK_TOP_NET1PLL_D8_D2 20
|
||||
#define CLK_TOP_NET1PLL_D8_D4 21
|
||||
#define CLK_TOP_NET1PLL_D8_D8 22
|
||||
#define CLK_TOP_NET1PLL_D8_D16 23
|
||||
#define CLK_TOP_NET2PLL_D2 24
|
||||
#define CLK_TOP_NET2PLL_D4 25
|
||||
#define CLK_TOP_NET2PLL_D4_D4 26
|
||||
#define CLK_TOP_NET2PLL_D4_D8 27
|
||||
#define CLK_TOP_NET2PLL_D6 28
|
||||
#define CLK_TOP_NET2PLL_D8 29
|
||||
/* mtk_mux */
|
||||
#define CK_TOP_NETSYS_SEL 30
|
||||
#define CK_TOP_NETSYS_500M_SEL 31
|
||||
#define CK_TOP_NETSYS_2X_SEL 32
|
||||
#define CK_TOP_NETSYS_GSW_SEL 33
|
||||
#define CK_TOP_ETH_GMII_SEL 34
|
||||
#define CK_TOP_NETSYS_MCU_SEL 35
|
||||
#define CK_TOP_NETSYS_PAO_2X_SEL 36
|
||||
#define CK_TOP_EIP197_SEL 37
|
||||
#define CK_TOP_AXI_INFRA_SEL 38
|
||||
#define CK_TOP_UART_SEL 39
|
||||
#define CK_TOP_EMMC_250M_SEL 40
|
||||
#define CK_TOP_EMMC_400M_SEL 41
|
||||
#define CK_TOP_SPI_SEL 42
|
||||
#define CK_TOP_SPIM_MST_SEL 43
|
||||
#define CK_TOP_NFI1X_SEL 44
|
||||
#define CK_TOP_SPINFI_SEL 45
|
||||
#define CK_TOP_PWM_SEL 46
|
||||
#define CK_TOP_I2C_SEL 47
|
||||
#define CK_TOP_PCIE_MBIST_250M_SEL 48
|
||||
#define CK_TOP_PEXTP_TL_SEL 49
|
||||
#define CK_TOP_PEXTP_TL_P1_SEL 50
|
||||
#define CK_TOP_PEXTP_TL_P2_SEL 51
|
||||
#define CK_TOP_PEXTP_TL_P3_SEL 52
|
||||
#define CK_TOP_USB_SYS_SEL 53
|
||||
#define CK_TOP_USB_SYS_P1_SEL 54
|
||||
#define CK_TOP_USB_XHCI_SEL 55
|
||||
#define CK_TOP_USB_XHCI_P1_SEL 56
|
||||
#define CK_TOP_USB_FRMCNT_SEL 57
|
||||
#define CK_TOP_USB_FRMCNT_P1_SEL 58
|
||||
#define CK_TOP_AUD_SEL 59
|
||||
#define CK_TOP_A1SYS_SEL 60
|
||||
#define CK_TOP_AUD_L_SEL 61
|
||||
#define CK_TOP_A_TUNER_SEL 62
|
||||
#define CK_TOP_SSPXTP_SEL 63
|
||||
#define CK_TOP_USB_PHY_SEL 64
|
||||
#define CK_TOP_USXGMII_SBUS_0_SEL 65
|
||||
#define CK_TOP_USXGMII_SBUS_1_SEL 66
|
||||
#define CK_TOP_SGM_0_SEL 67
|
||||
#define CK_TOP_SGM_SBUS_0_SEL 68
|
||||
#define CK_TOP_SGM_1_SEL 69
|
||||
#define CK_TOP_SGM_SBUS_1_SEL 70
|
||||
#define CK_TOP_XFI_PHY_0_XTAL_SEL 71
|
||||
#define CK_TOP_XFI_PHY_1_XTAL_SEL 72
|
||||
#define CK_TOP_SYSAXI_SEL 73
|
||||
#define CK_TOP_SYSAPB_SEL 74
|
||||
#define CK_TOP_ETH_REFCK_50M_SEL 75
|
||||
#define CK_TOP_ETH_SYS_200M_SEL 76
|
||||
#define CK_TOP_ETH_SYS_SEL 77
|
||||
#define CK_TOP_ETH_XGMII_SEL 78
|
||||
#define CK_TOP_BUS_TOPS_SEL 79
|
||||
#define CK_TOP_NPU_TOPS_SEL 80
|
||||
#define CK_TOP_DRAMC_SEL 81
|
||||
#define CK_TOP_DRAMC_MD32_SEL 82
|
||||
#define CK_TOP_INFRA_F26M_SEL 83
|
||||
#define CK_TOP_PEXTP_P0_SEL 84
|
||||
#define CK_TOP_PEXTP_P1_SEL 85
|
||||
#define CK_TOP_PEXTP_P2_SEL 86
|
||||
#define CK_TOP_PEXTP_P3_SEL 87
|
||||
#define CK_TOP_DA_XTP_GLB_P0_SEL 88
|
||||
#define CK_TOP_DA_XTP_GLB_P1_SEL 89
|
||||
#define CK_TOP_DA_XTP_GLB_P2_SEL 90
|
||||
#define CK_TOP_DA_XTP_GLB_P3_SEL 91
|
||||
#define CK_TOP_CKM_SEL 92
|
||||
#define CK_TOP_DA_SEL 93
|
||||
#define CK_TOP_PEXTP_SEL 94
|
||||
#define CK_TOP_TOPS_P2_26M_SEL 95
|
||||
#define CK_TOP_MCUSYS_BACKUP_625M_SEL 96
|
||||
#define CK_TOP_NETSYS_SYNC_250M_SEL 97
|
||||
#define CK_TOP_MACSEC_SEL 98
|
||||
#define CK_TOP_NETSYS_TOPS_400M_SEL 99
|
||||
#define CK_TOP_NETSYS_PPEFB_250M_SEL 100
|
||||
#define CK_TOP_NETSYS_WARP_SEL 101
|
||||
#define CK_TOP_ETH_MII_SEL 102
|
||||
#define CK_TOP_NPU_SEL 103
|
||||
#define CLK_TOP_NETSYS_SEL 30
|
||||
#define CLK_TOP_NETSYS_500M_SEL 31
|
||||
#define CLK_TOP_NETSYS_2X_SEL 32
|
||||
#define CLK_TOP_NETSYS_GSW_SEL 33
|
||||
#define CLK_TOP_ETH_GMII_SEL 34
|
||||
#define CLK_TOP_NETSYS_MCU_SEL 35
|
||||
#define CLK_TOP_NETSYS_PAO_2X_SEL 36
|
||||
#define CLK_TOP_EIP197_SEL 37
|
||||
#define CLK_TOP_AXI_INFRA_SEL 38
|
||||
#define CLK_TOP_UART_SEL 39
|
||||
#define CLK_TOP_EMMC_250M_SEL 40
|
||||
#define CLK_TOP_EMMC_400M_SEL 41
|
||||
#define CLK_TOP_SPI_SEL 42
|
||||
#define CLK_TOP_SPIM_MST_SEL 43
|
||||
#define CLK_TOP_NFI1X_SEL 44
|
||||
#define CLK_TOP_SPINFI_SEL 45
|
||||
#define CLK_TOP_PWM_SEL 46
|
||||
#define CLK_TOP_I2C_SEL 47
|
||||
#define CLK_TOP_PCIE_MBIST_250M_SEL 48
|
||||
#define CLK_TOP_PEXTP_TL_SEL 49
|
||||
#define CLK_TOP_PEXTP_TL_P1_SEL 50
|
||||
#define CLK_TOP_PEXTP_TL_P2_SEL 51
|
||||
#define CLK_TOP_PEXTP_TL_P3_SEL 52
|
||||
#define CLK_TOP_USB_SYS_SEL 53
|
||||
#define CLK_TOP_USB_SYS_P1_SEL 54
|
||||
#define CLK_TOP_USB_XHCI_SEL 55
|
||||
#define CLK_TOP_USB_XHCI_P1_SEL 56
|
||||
#define CLK_TOP_USB_FRMCNT_SEL 57
|
||||
#define CLK_TOP_USB_FRMCNT_P1_SEL 58
|
||||
#define CLK_TOP_AUD_SEL 59
|
||||
#define CLK_TOP_A1SYS_SEL 60
|
||||
#define CLK_TOP_AUD_L_SEL 61
|
||||
#define CLK_TOP_A_TUNER_SEL 62
|
||||
#define CLK_TOP_SSPXTP_SEL 63
|
||||
#define CLK_TOP_USB_PHY_SEL 64
|
||||
#define CLK_TOP_USXGMII_SBUS_0_SEL 65
|
||||
#define CLK_TOP_USXGMII_SBUS_1_SEL 66
|
||||
#define CLK_TOP_SGM_0_SEL 67
|
||||
#define CLK_TOP_SGM_SBUS_0_SEL 68
|
||||
#define CLK_TOP_SGM_1_SEL 69
|
||||
#define CLK_TOP_SGM_SBUS_1_SEL 70
|
||||
#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
|
||||
#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
|
||||
#define CLK_TOP_SYSAXI_SEL 73
|
||||
#define CLK_TOP_SYSAPB_SEL 74
|
||||
#define CLK_TOP_ETH_REFCK_50M_SEL 75
|
||||
#define CLK_TOP_ETH_SYS_200M_SEL 76
|
||||
#define CLK_TOP_ETH_SYS_SEL 77
|
||||
#define CLK_TOP_ETH_XGMII_SEL 78
|
||||
#define CLK_TOP_BUS_TOPS_SEL 79
|
||||
#define CLK_TOP_NPU_TOPS_SEL 80
|
||||
#define CLK_TOP_DRAMC_SEL 81
|
||||
#define CLK_TOP_DRAMC_MD32_SEL 82
|
||||
#define CLK_TOP_INFRA_F26M_SEL 83
|
||||
#define CLK_TOP_PEXTP_P0_SEL 84
|
||||
#define CLK_TOP_PEXTP_P1_SEL 85
|
||||
#define CLK_TOP_PEXTP_P2_SEL 86
|
||||
#define CLK_TOP_PEXTP_P3_SEL 87
|
||||
#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
|
||||
#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
|
||||
#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
|
||||
#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
|
||||
#define CLK_TOP_CKM_SEL 92
|
||||
#define CLK_TOP_DA_SEL 93
|
||||
#define CLK_TOP_PEXTP_SEL 94
|
||||
#define CLK_TOP_TOPS_P2_26M_SEL 95
|
||||
#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
|
||||
#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
|
||||
#define CLK_TOP_MACSEC_SEL 98
|
||||
#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
|
||||
#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
|
||||
#define CLK_TOP_NETSYS_WARP_SEL 101
|
||||
#define CLK_TOP_ETH_MII_SEL 102
|
||||
#define CLK_TOP_NPU_SEL 103
|
||||
|
||||
/* APMIXEDSYS */
|
||||
/* mtk_pll_data */
|
||||
#define CK_APMIXED_NETSYSPLL 0
|
||||
#define CK_APMIXED_MPLL 1
|
||||
#define CK_APMIXED_MMPLL 2
|
||||
#define CK_APMIXED_APLL2 3
|
||||
#define CK_APMIXED_NET1PLL 4
|
||||
#define CK_APMIXED_NET2PLL 5
|
||||
#define CK_APMIXED_WEDMCUPLL 6
|
||||
#define CK_APMIXED_SGMPLL 7
|
||||
#define CK_APMIXED_ARM_B 8
|
||||
#define CK_APMIXED_CCIPLL2_B 9
|
||||
#define CK_APMIXED_USXGMIIPLL 10
|
||||
#define CK_APMIXED_MSDCPLL 11
|
||||
#define CLK_APMIXED_NETSYSPLL 0
|
||||
#define CLK_APMIXED_MPLL 1
|
||||
#define CLK_APMIXED_MMPLL 2
|
||||
#define CLK_APMIXED_APLL2 3
|
||||
#define CLK_APMIXED_NET1PLL 4
|
||||
#define CLK_APMIXED_NET2PLL 5
|
||||
#define CLK_APMIXED_WEDMCUPLL 6
|
||||
#define CLK_APMIXED_SGMPLL 7
|
||||
#define CLK_APMIXED_ARM_B 8
|
||||
#define CLK_APMIXED_CCIPLL2_B 9
|
||||
#define CLK_APMIXED_USXGMIIPLL 10
|
||||
#define CLK_APMIXED_MSDCPLL 11
|
||||
|
||||
/* ETHSYS ETH DMA */
|
||||
/* mtk_gate */
|
||||
#define CK_ETHDMA_FE_EN 0
|
||||
#define CLK_ETHDMA_FE_EN 0
|
||||
|
||||
/* SGMIISYS_0 */
|
||||
/* mtk_gate */
|
||||
#define CK_SGM0_TX_EN 0
|
||||
#define CK_SGM0_RX_EN 1
|
||||
#define CLK_SGM0_TX_EN 0
|
||||
#define CLK_SGM0_RX_EN 1
|
||||
|
||||
/* SGMIISYS_1 */
|
||||
/* mtk_gate */
|
||||
#define CK_SGM1_TX_EN 0
|
||||
#define CK_SGM1_RX_EN 1
|
||||
#define CLK_SGM1_TX_EN 0
|
||||
#define CLK_SGM1_RX_EN 1
|
||||
|
||||
/* ETHWARP */
|
||||
/* mtk_gate */
|
||||
#define CK_ETHWARP_WOCPU2_EN 0
|
||||
#define CK_ETHWARP_WOCPU1_EN 1
|
||||
#define CK_ETHWARP_WOCPU0_EN 2
|
||||
#define CLK_ETHWARP_WOCPU2_EN 0
|
||||
#define CLK_ETHWARP_WOCPU1_EN 1
|
||||
#define CLK_ETHWARP_WOCPU0_EN 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7988_H */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue