x86: select CONFIG_64BIT for X86_64

Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to
static analysis tools.
Introduce CONFIG_SPL_64BIT and select it for architectures other than
x86 with 64 bit builds. Do not select it for x86 builds as x86 uses
a 32 bit SPL.
Ensure that when limits are set they use CONFIG_64BIT for U-Boot
proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit
SPL build used by x86.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
This commit is contained in:
Andrew Goodbody 2024-12-16 18:07:35 +00:00 committed by Tom Rini
parent bcb9b3524a
commit 99145eec2d
8 changed files with 26 additions and 6 deletions

View file

@ -37,6 +37,14 @@ config 32BIT
config 64BIT
bool
help
Indicates that U-Boot proper will be built for a 64 bit
architecture.
config SPL_64BIT
bool
help
Indicates that SPL will be built for a 64 bit architecture.
config SYS_CACHELINE_SIZE
int

View file

@ -7,6 +7,7 @@ config SYS_ARCH
config ARM64
bool
select 64BIT
select SPL_64BIT if SPL
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS

View file

@ -211,6 +211,7 @@ config CPU_MIPS64_R1
bool "MIPS64 Release 1"
depends on SUPPORTS_CPU_MIPS64_R1
select 64BIT
select SPL_64BIT if SPL
help
Choose this option to build a kernel for release 1 through 5 of the
MIPS64 architecture.
@ -219,6 +220,7 @@ config CPU_MIPS64_R2
bool "MIPS64 Release 2"
depends on SUPPORTS_CPU_MIPS64_R2
select 64BIT
select SPL_64BIT if SPL
help
Choose this option to build a kernel for release 2 through 5 of the
MIPS64 architecture.
@ -227,6 +229,7 @@ config CPU_MIPS64_R6
bool "MIPS64 Release 6"
depends on SUPPORTS_CPU_MIPS64_R6
select 64BIT
select SPL_64BIT if SPL
help
Choose this option to build a kernel for release 6 or later of the
MIPS64 architecture.
@ -235,6 +238,7 @@ config CPU_MIPS64_OCTEON
bool "Marvell Octeon series of CPUs"
depends on SUPPORTS_CPU_MIPS64_OCTEON
select 64BIT
select SPL_64BIT if SPL
help
Choose this option for Marvell Octeon CPUs. These CPUs are between
MIPS64 R5 and R6 with other extensions.

View file

@ -120,6 +120,7 @@ config ARCH_RV32I
config ARCH_RV64I
bool "RV64I"
select 64BIT
select SPL_64BIT if SPL
select PHYS_64BIT
help
Choose this option to target the RV64I base integer instruction set.

View file

@ -47,6 +47,7 @@ config HOST_32BIT
config HOST_64BIT
def_bool $(cc-define,_LP64)
select 64BIT
select SPL_64BIT if SPL
config HOST_HAS_SDL
def_bool $(success,sdl2-config --version)

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@ -44,6 +44,7 @@ endchoice
config X86_64
bool
select 64BIT
config SPL_X86_64
bool

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@ -576,14 +576,17 @@ int bloblist_maybe_init(void)
int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig)
{
ulong version = BLOBLIST_REGCONV_VER;
u64 version = BLOBLIST_REGCONV_VER;
ulong sigval;
sigval = (IS_ENABLED(CONFIG_64BIT)) ?
((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_64) - 1)) |
((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64)) :
((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) |
if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) ||
(IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) {
sigval = ((BLOBLIST_MAGIC & ((1ULL << BLOBLIST_REGCONV_SHIFT_64) - 1)) |
((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_64));
} else {
sigval = ((BLOBLIST_MAGIC & ((1UL << BLOBLIST_REGCONV_SHIFT_32) - 1)) |
((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32));
}
if (rzero || rsig != sigval ||
rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {

View file

@ -9,7 +9,8 @@
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffULL
#ifdef CONFIG_64BIT
#if (defined(CONFIG_64BIT) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_64BIT) && defined(CONFIG_SPL_BUILD))
#define UINTPTR_MAX UINT64_MAX
#else
#define UINTPTR_MAX UINT32_MAX