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ARM: dts: stm32: Add STM32MP257F Evaluation board support
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... Sync device tree with kernel v6.6-rc1. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Patrice Chotard
parent
778f4eaa80
commit
970d1673b0
15 changed files with 788 additions and 0 deletions
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@ -1352,6 +1352,9 @@ dtb-$(CONFIG_STM32MP15x) += \
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stm32mp15xx-dhcor-drc-compact.dtb \
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stm32mp15xx-dhcor-testbench.dtb
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dtb-$(CONFIG_STM32MP25X) += \
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stm32mp257f-ev1.dtb
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dtb-$(CONFIG_SOC_K3_AM654) += \
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k3-am654-base-board.dtb \
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k3-am654-r5-base-board.dtb \
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38
arch/arm/dts/stm32mp25-pinctrl.dtsi
Normal file
38
arch/arm/dts/stm32mp25-pinctrl.dtsi
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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usart2_pins_a: usart2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
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bias-disable;
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};
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};
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usart2_idle_pins_a: usart2-idle-0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
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bias-disable;
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};
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};
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usart2_sleep_pins_a: usart2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
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<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
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};
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};
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};
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102
arch/arm/dts/stm32mp25-u-boot.dtsi
Normal file
102
arch/arm/dts/stm32mp25-u-boot.dtsi
Normal file
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@ -0,0 +1,102 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2023
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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pinctrl0 = &pinctrl;
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pinctrl1 = &pinctrl_z;
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};
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firmware {
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optee {
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bootph-all;
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};
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};
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/* need PSCI for sysreset during board_f */
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psci {
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bootph-all;
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};
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soc@0 {
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bootph-all;
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};
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};
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&gpioa {
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bootph-all;
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};
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&gpiob {
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bootph-all;
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};
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&gpioc {
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bootph-all;
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};
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&gpiod {
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bootph-all;
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};
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&gpioe {
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bootph-all;
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};
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&gpiof {
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bootph-all;
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};
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&gpiog {
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bootph-all;
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};
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&gpioh {
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bootph-all;
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};
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&gpioi {
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bootph-all;
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};
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&gpioj {
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bootph-all;
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};
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&gpiok {
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bootph-all;
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};
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&gpioz {
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bootph-all;
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};
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&pinctrl {
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bootph-all;
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};
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&rifsc {
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bootph-all;
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};
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&scmi_clk {
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bootph-all;
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};
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&syscfg {
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bootph-all;
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};
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285
arch/arm/dts/stm32mp251.dtsi
Normal file
285
arch/arm/dts/stm32mp251.dtsi
Normal file
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@ -0,0 +1,285 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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interrupt-parent = <&intc>;
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};
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arm_wdt: watchdog {
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compatible = "arm,smc-wdt";
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arm,smc-id = <0xb200005a>;
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status = "disabled";
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};
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clocks {
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ck_flexgen_08: ck-flexgen-08 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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ck_flexgen_51: ck-flexgen-51 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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ck_icn_ls_mcu: ck-icn-ls-mcu {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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};
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intc: interrupt-controller@4ac00000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x0 0x4ac10000 0x0 0x1000>,
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<0x0 0x4ac20000 0x0 0x2000>,
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<0x0 0x4ac40000 0x0 0x2000>,
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<0x0 0x4ac60000 0x0 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0x0 0x0 0x0 0x80000000>;
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rifsc: rifsc-bus@42080000 {
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compatible = "simple-bus";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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status = "disabled";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp25-syscfg", "syscon";
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reg = <0x44230000 0x10000>;
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};
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pinctrl: pinctrl@44240000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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pins-are-numbered;
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gpioa: gpio@44240000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@44250000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOB";
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status = "disabled";
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};
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gpioc: gpio@44260000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x20000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOC";
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status = "disabled";
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};
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gpiod: gpio@44270000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x30000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOD";
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status = "disabled";
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};
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gpioe: gpio@44280000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x40000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOE";
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status = "disabled";
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};
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gpiof: gpio@44290000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x50000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOF";
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status = "disabled";
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};
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gpiog: gpio@442a0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x60000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOG";
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status = "disabled";
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};
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gpioh: gpio@442b0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x70000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOH";
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status = "disabled";
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};
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gpioi: gpio@442c0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x80000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOI";
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status = "disabled";
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};
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gpioj: gpio@442d0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x90000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOJ";
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status = "disabled";
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};
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gpiok: gpio@442e0000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xa0000 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOK";
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status = "disabled";
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};
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};
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pinctrl_z: pinctrl@46200000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-z-pinctrl";
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ranges = <0 0x46200000 0x400>;
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pins-are-numbered;
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gpioz: gpio@46200000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x400>;
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clocks = <&ck_icn_ls_mcu>;
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st,bank-name = "GPIOZ";
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st,bank-ioport = <11>;
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status = "disabled";
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};
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};
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};
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};
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23
arch/arm/dts/stm32mp253.dtsi
Normal file
23
arch/arm/dts/stm32mp253.dtsi
Normal file
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@ -0,0 +1,23 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp251.dtsi"
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/ {
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cpus {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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};
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arm-pmu {
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interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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};
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9
arch/arm/dts/stm32mp255.dtsi
Normal file
9
arch/arm/dts/stm32mp255.dtsi
Normal file
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@ -0,0 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
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*/
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#include "stm32mp253.dtsi"
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/ {
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};
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9
arch/arm/dts/stm32mp257.dtsi
Normal file
9
arch/arm/dts/stm32mp257.dtsi
Normal file
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@ -0,0 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
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*/
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#include "stm32mp255.dtsi"
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/ {
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};
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||||
20
arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
Normal file
20
arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
*/
|
||||
|
||||
#include "stm32mp25-u-boot.dtsi"
|
||||
|
||||
&usart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&usart2_pins_a {
|
||||
bootph-all;
|
||||
pins1 {
|
||||
bootph-all;
|
||||
};
|
||||
pins2 {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
55
arch/arm/dts/stm32mp257f-ev1.dts
Normal file
55
arch/arm/dts/stm32mp257f-ev1.dts
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp257.dtsi"
|
||||
#include "stm32mp25xf.dtsi"
|
||||
#include "stm32mp25-pinctrl.dtsi"
|
||||
#include "stm32mp25xxai-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
|
||||
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
|
||||
|
||||
aliases {
|
||||
serial0 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x0>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
fw@80000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x80000000 0x0 0x4000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&arm_wdt {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "idle", "sleep";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
pinctrl-1 = <&usart2_idle_pins_a>;
|
||||
pinctrl-2 = <&usart2_sleep_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
8
arch/arm/dts/stm32mp25xc.dtsi
Normal file
8
arch/arm/dts/stm32mp25xc.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
8
arch/arm/dts/stm32mp25xf.dtsi
Normal file
8
arch/arm/dts/stm32mp25xf.dtsi
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
83
arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
Normal file
83
arch/arm/dts/stm32mp25xxai-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AI>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@442d0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@442e0000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
71
arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
Normal file
71
arch/arm/dts/stm32mp25xxak-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AK>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
71
arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Normal file
71
arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AL>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
|
|
@ -37,6 +37,9 @@
|
|||
#define STM32MP_PKG_AB 0x2
|
||||
#define STM32MP_PKG_AC 0x4
|
||||
#define STM32MP_PKG_AD 0x8
|
||||
#define STM32MP_PKG_AI 0x100
|
||||
#define STM32MP_PKG_AK 0x400
|
||||
#define STM32MP_PKG_AL 0x800
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue