Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-20 11:55:03 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARM: zynq: DT: Enable all FCLKs by default

Browse source 
The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.

Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b1308dc1f14f8eb24662019f7376c959e5e763b8.1665567031.git.michal.simek@amd.com
This commit is contained in:
Christian Kohn 2022-10-12 11:30:33 +02:00 • committed by Michal Simek
parent b34bc22bd9
commit 96dcde487e
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/zynq-7000.dtsi
View file

@ -340,7 +340,7 @@
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
#clock-cells = <1>; #clock-cells = <1>;
compatible = "xlnx,ps7-clkc"; compatible = "xlnx,ps7-clkc";
fclk-enable = <0>; fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1", "dci", "lqspi", "smc", "pcap", "gem0", "gem1",