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arm: include: imx: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-13 15:19:00 +02:00 • committed by Tom Rini
parent 59ccc9c83b
commit 9671f49116
13 changed files with 0 additions and 22 deletions
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1
arch/arm/include/asm/arch-mx27/gpio.h
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@ -4,7 +4,6 @@
* Philippe Reynes <tremyfr@yahoo.fr> * Philippe Reynes <tremyfr@yahoo.fr>
*/ */
#ifndef __ASM_ARCH_MX27_GPIO_H #ifndef __ASM_ARCH_MX27_GPIO_H
#define __ASM_ARCH_MX27_GPIO_H #define __ASM_ARCH_MX27_GPIO_H

1
arch/arm/include/asm/arch-mx27/imx-regs.h
View file

@ -236,7 +236,6 @@ struct fuse_bank0_regs {
#define SDCS1_SEL (1 << 1) #define SDCS1_SEL (1 << 1)
#define SDCS0_SEL (1 << 0) #define SDCS0_SEL (1 << 0)
/* important definition of some bits of WCR */ /* important definition of some bits of WCR */
#define WCR_WDE 0x04 #define WCR_WDE 0x04

1
arch/arm/include/asm/arch-mx31/gpio.h
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@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de> * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/ */
#ifndef __ASM_ARCH_MX31_GPIO_H #ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H #define __ASM_ARCH_MX31_GPIO_H

2
arch/arm/include/asm/arch-mx31/imx-regs.h
View file

@ -585,7 +585,6 @@ struct esdc_regs {
#define GET_PLL_MFI(x) (((x) >> 10) & 0xf) #define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
#define WEIM_ESDCTL0 0xB8001000 #define WEIM_ESDCTL0 0xB8001000
#define WEIM_ESDCFG0 0xB8001004 #define WEIM_ESDCFG0 0xB8001004
#define WEIM_ESDCTL1 0xB8001008 #define WEIM_ESDCTL1 0xB8001008
@ -777,7 +776,6 @@ struct esdc_regs {
#define MUX_CTL_NFC_ALE 0xD6 #define MUX_CTL_NFC_ALE 0xD6
#define MUX_CTL_NFC_CLE 0xD7 #define MUX_CTL_NFC_CLE 0xD7
#define MUX_CTL_CAPTURE 0x150 #define MUX_CTL_CAPTURE 0x150
#define MUX_CTL_COMPARE 0x151 #define MUX_CTL_COMPARE 0x151

1
arch/arm/include/asm/arch-mx5/gpio.h
View file

@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de> * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/ */
#ifndef __ASM_ARCH_MX5_GPIO_H #ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H #define __ASM_ARCH_MX5_GPIO_H

1
arch/arm/include/asm/arch-mx6/gpio.h
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@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de> * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/ */
#ifndef __ASM_ARCH_MX6_GPIO_H #ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H #define __ASM_ARCH_MX6_GPIO_H

1
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -385,7 +385,6 @@
((is_mx6ull()) ? \ ((is_mx6ull()) ? \
MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14 #define SRC_SCR_CORE_1_RESET_OFFSET 14

4
arch/arm/include/asm/arch-mx7/crm_regs.h
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@ -229,7 +229,6 @@ struct mxc_ccm_anatop_reg {
#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) #define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5)
#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) #define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12)
#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f #define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f
#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B
#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016
@ -1784,7 +1783,6 @@ struct mxc_ccm_anatop_reg {
#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24
#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
/* HW_ANADIG_TEMPSENSE0 Bit Fields */ /* HW_ANADIG_TEMPSENSE0 Bit Fields */
#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
@ -1998,7 +1996,6 @@ struct mxc_ccm_anatop_reg {
#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) #define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) #define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
@ -2091,7 +2088,6 @@ struct mxc_ccm_anatop_reg {
#define CLK_ROOT_ALT6 0x06000000 #define CLK_ROOT_ALT6 0x06000000
#define CLK_ROOT_ALT7 0x07000000 #define CLK_ROOT_ALT7 0x07000000
#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 #define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007
#define CLK_ROOT_POST_DIV_MASK 0x0000003f #define CLK_ROOT_POST_DIV_MASK 0x0000003f
#define CLK_ROOT_POST_DIV_SHIFT 0 #define CLK_ROOT_POST_DIV_SHIFT 0

2
arch/arm/include/asm/arch-mx7/imx-regs.h
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@ -71,7 +71,6 @@
#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
/* Defines for Blocks connected via AIPS (SkyBlue) */ /* Defines for Blocks connected via AIPS (SkyBlue) */
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
@ -1162,7 +1161,6 @@ struct rdc_sema_regs {
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
extern void check_cpu_temperature(void); extern void check_cpu_temperature(void);
extern void pcie_power_up(void); extern void pcie_power_up(void);

2
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View file

@ -124,7 +124,6 @@
#define IOMUXC_PSMI_IMUX_ALT6 (0x6) #define IOMUXC_PSMI_IMUX_ALT6 (0x6)
#define IOMUXC_PSMI_IMUX_ALT7 (0x7) #define IOMUXC_PSMI_IMUX_ALT7 (0x7)
#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8)
#define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
#define SIM_SOPT1_A7_SW_RESET (1<<0) #define SIM_SOPT1_A7_SW_RESET (1<<0)
@ -240,7 +239,6 @@
#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))
#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35)))
#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0)))
#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1)))
#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2)))

2
arch/arm/include/asm/arch-mx7ulp/iomux.h
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@ -69,7 +69,6 @@ typedef u64 iomux_cfg_t;
#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
MUX_PAD_CTRL(pad)) MUX_PAD_CTRL(pad))
#define IOMUX_CONFIG_MPORTS 0x20 #define IOMUX_CONFIG_MPORTS 0x20
#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT) MUX_MODE_SHIFT)
@ -87,7 +86,6 @@ typedef u64 iomux_cfg_t;
#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
unsigned count); unsigned count);

3
arch/arm/include/asm/arch-mx7ulp/pcc.h
View file

@ -278,7 +278,6 @@ enum pcc3_entry {
RSVD127_PCC3_SLOT = 127, RSVD127_PCC3_SLOT = 127,
}; };
/* PCC registers */ /* PCC registers */
#define PCC_PR_OFFSET 31 #define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) #define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
@ -293,7 +292,6 @@ enum pcc3_entry {
#define PCC_PCD_OFFSET 0 #define PCC_PCD_OFFSET 0
#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) #define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type { enum pcc_clksrc_type {
CLKSRC_PER_PLAT = 0, CLKSRC_PER_PLAT = 0,
CLKSRC_PER_BUS = 1, CLKSRC_PER_BUS = 1,
@ -353,7 +351,6 @@ enum pcc_clk {
PER_CLK_GPU2D, PER_CLK_GPU2D,
}; };
/* This structure keeps info for each pcc slot */ /* This structure keeps info for each pcc slot */
struct pcc_entry { struct pcc_entry {
u32 pcc_base; u32 pcc_base;

1
arch/arm/include/asm/arch-mx7ulp/scg.h
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@ -145,7 +145,6 @@
#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) #define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
#define SCG_PLL_PFD3_GATE_MASK (0x80000000) #define SCG_PLL_PFD3_GATE_MASK (0x80000000)
#define SCG_PLL_PFD2_GATE_MASK (0x00800000) #define SCG_PLL_PFD2_GATE_MASK (0x00800000)
#define SCG_PLL_PFD1_GATE_MASK (0x00008000) #define SCG_PLL_PFD1_GATE_MASK (0x00008000)