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Merge tag 'u-boot-rockchip-20200722' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse source 
- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;
This commit is contained in:
Tom Rini 2020-07-22 11:30:52 -04:00
commit 95fc1f1647
61 changed files with 2180 additions and 610 deletions
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7
arch/arm/dts/Makefile
View file

@ -71,7 +71,8 @@ dtb-$(CONFIG_MACH_S700) += \
dtb-$(CONFIG_ROCKCHIP_PX30) += \
px30-evb.dtb \
px30-firefly.dtb
px30-firefly.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
@ -135,7 +136,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4b.dtb \
rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb

2
arch/arm/dts/rk3288-rock-pi-n8.dts
View file

@ -7,8 +7,8 @@
/dts-v1/;
#include "rk3288.dtsi"
#include "rk3288-vmarc-som.dtsi"
#include <rockchip-radxa-dalang-carrier.dtsi>
#include "rk3288-vmarc-som.dtsi"
/ {
model = "Radxa ROCK Pi N8";

132
arch/arm/dts/rk3288-vmarc-som.dtsi
View file

@ -7,35 +7,17 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
/ {
compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288";
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
#clock-cells = <0>;
};
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_flash";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <150>;
vin-supply = <&vcc_io>;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
};
&emmc {
@ -45,23 +27,21 @@
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
phy-mode = "rgmii";
phy-supply = <&vcc_io>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
max-speed = <1000>;
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec_c0>;
};
&i2c0 {
@ -80,37 +60,37 @@
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc_io>;
vcc9-supply = <&vcc_io>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc_io>;
vddio-supply = <&vcc_io>;
regulators {
vdd_cpu: DCDC_REG1 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd_gpu";
regulator-ramp-delay = <6000>;
regulator-state-mem {
regulator-off-in-suspend;
@ -118,20 +98,20 @@
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@ -139,22 +119,22 @@
};
vcc_tp: LDO_REG1 {
regulator-name = "vcc_tp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_codec: LDO_REG2 {
regulator-name = "vcca_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_codec";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@ -162,11 +142,11 @@
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@ -174,22 +154,22 @@
};
vcc_wl: LDO_REG4 {
regulator-name = "vcc_wl";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_wl";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
@ -197,22 +177,22 @@
};
vdd10_lcd: LDO_REG6 {
regulator-name = "vdd10_lcd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_18: LDO_REG7 {
regulator-name = "vcc_18";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -220,29 +200,29 @@
};
vcc18_lcd: LDO_REG8 {
regulator-name = "vcc18_lcd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sd: SWITCH_REG1 {
regulator-name = "vcc_sd";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_lcd: SWITCH_REG2 {
regulator-name = "vcc_lcd";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_lcd";
regulator-state-mem {
regulator-off-in-suspend;
};
@ -251,6 +231,10 @@
};
};
&i2c5 {
status = "okay";
};
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
drive-strength = <8>;
@ -277,13 +261,53 @@
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
};
};
vbus_host {
usb1_en_oc: usb1-en-oc {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
vbus_typec {
usb0_en_oc: usb0-en-oc {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&usbphy {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1 {
status = "okay";
};
&usb_otg {
status = "okay";
};
&vbus_host {
enable-active-high;
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
};
&vbus_typec {
enable-active-high;
gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
};

17
arch/arm/dts/rk3288.dtsi
View file

@ -431,7 +431,16 @@
status = "disabled";
};
/* NOTE: ohci@ff520000 doesn't actually work on hardware */
/* NOTE: doesn't work on RK3288, but fixed on RK3288W */
usb_host0_ohci: usb@ff520000 {
compatible = "generic-ohci";
reg = <0x0 0xff520000 0x0 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>;
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
};
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
@ -1085,6 +1094,12 @@
#interrupt-cells = <2>;
};
hdmi {
hdmi_cec_c0: hdmi-cec-c0 {
rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
};
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};

72
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi Normal file
View file

@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
/ {
chosen {
u-boot,spl-boot-order = &sdmmc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&dmc {
u-boot,dm-pre-reloc;
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&uart1 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};

716
arch/arm/dts/rk3326-odroid-go2.dts Normal file
View file

@ -0,0 +1,716 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Hardkernel Co., Ltd
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3326.dtsi"
/ {
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
chosen {
stdout-path = "serial2:115200n8";
};
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc_bl>;
pwms = <&pwm1 0 25000 0>;
};
adc-joystick {
compatible = "adc-joystick";
io-channels = <&saradc 1>,
<&saradc 2>;
#address-cells = <1>;
#size-cells = <0>;
axis@0 {
reg = <0>;
abs-range = <172 772>;
abs-fuzz = <10>;
abs-flat = <10>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
abs-range = <278 815>;
abs-fuzz = <10>;
abs-flat = <10>;
linux,code = <ABS_Y>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&btn_pins>;
/*
* *** ODROIDGO2-Advance Switch layout ***
* |------------------------------------------------|
* | sw15 sw16 |
* |------------------------------------------------|
* | sw1 |-------------------| sw8 |
* | sw3 sw4 | | sw7 sw5 |
* | sw2 | LCD Display | sw6 |
* | | | |
* | |-------------------| |
* | sw9 sw10 sw11 sw12 sw13 sw14 |
* |------------------------------------------------|
*/
sw1 {
gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
sw2 {
gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
sw3 {
gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
label = "DPAD-LEFT";
linux,code = <BTN_DPAD_LEFT>;
};
sw4 {
gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
label = "DPAD-RIGHT";
linux,code = <BTN_DPAD_RIGHT>;
};
sw5 {
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
label = "BTN-A";
linux,code = <BTN_EAST>;
};
sw6 {
gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
label = "BTN-B";
linux,code = <BTN_SOUTH>;
};
sw7 {
gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
label = "BTN-Y";
linux,code = <BTN_WEST>;
};
sw8 {
gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
label = "BTN-X";
linux,code = <BTN_NORTH>;
};
sw9 {
gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
label = "F1";
linux,code = <BTN_TRIGGER_HAPPY1>;
};
sw10 {
gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
label = "F2";
linux,code = <BTN_TRIGGER_HAPPY2>;
};
sw11 {
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
label = "F3";
linux,code = <BTN_TRIGGER_HAPPY3>;
};
sw12 {
gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
label = "F4";
linux,code = <BTN_TRIGGER_HAPPY4>;
};
sw13 {
gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
label = "F5";
linux,code = <BTN_TRIGGER_HAPPY5>;
};
sw14 {
gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
label = "F6";
linux,code = <BTN_TRIGGER_HAPPY6>;
};
sw15 {
gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
label = "TOP-LEFT";
linux,code = <BTN_TL>;
};
sw16 {
gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
label = "TOP-RIGHT";
linux,code = <BTN_TR>;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&blue_led_pin>;
blue_led: led-0 {
label = "blue:heartbeat";
gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
rk817-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rk817-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
simple-audio-card,codec-hp-det = <1>;
simple-audio-card,cpu {
sound-dai = <&i2s1_2ch>;
};
simple-audio-card,codec {
sound-dai = <&rk817_codec>;
};
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
regulator-always-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
vcc_host: vcc_host {
compatible = "regulator-fixed";
regulator-name = "vcc_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
vin-supply = <&vccsys>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&cru {
assigned-clocks = <&cru PLL_NPLL>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
<&cru PLL_CPLL>;
assigned-clock-rates = <1188000000>,
<200000000>, <200000000>,
<150000000>, <150000000>,
<100000000>, <200000000>,
<17000000>;
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
ports {
mipi_out: port@1 {
reg = <1>;
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};
};
panel@0 {
compatible = "elida,kd35t133";
reg = <0>;
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc_lcd>;
port {
mipi_in_panel: endpoint {
remote-endpoint = <&mipi_out_panel>;
};
};
};
};
&dsi_dphy {
status = "okay";
};
&gpu {
mali-supply = <&vdd_logic>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <16>;
i2c-scl-rising-time-ns = <280>;
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default", "pmic-sleep",
"pmic-power-off", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "xin32k";
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
vcc3-supply = <&vccsys>;
vcc4-supply = <&vccsys>;
vcc5-supply = <&vccsys>;
vcc6-supply = <&vccsys>;
vcc7-supply = <&vccsys>;
pinctrl_rk8xx: pinctrl_rk8xx {
gpio-controller;
#gpio-cells = <2>;
rk817_ts_gpio1: rk817_ts_gpio1 {
pins = "gpio_ts";
function = "pin_fun1";
/* output-low; */
/* input-enable; */
};
rk817_gt_gpio2: rk817_gt_gpio2 {
pins = "gpio_gt";
function = "pin_fun1";
};
rk817_pin_ts: rk817_pin_ts {
pins = "gpio_ts";
function = "pin_fun0";
};
rk817_pin_gt: rk817_pin_gt {
pins = "gpio_gt";
function = "pin_fun0";
};
rk817_slppin_null: rk817_slppin_null {
pins = "gpio_slp";
function = "pin_fun0";
};
rk817_slppin_slp: rk817_slppin_slp {
pins = "gpio_slp";
function = "pin_fun1";
};
rk817_slppin_pwrdn: rk817_slppin_pwrdn {
pins = "gpio_slp";
function = "pin_fun2";
};
rk817_slppin_rst: rk817_slppin_rst {
pins = "gpio_slp";
function = "pin_fun3";
};
};
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8: LDO_REG2 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_1v0: LDO_REG3 {
regulator-name = "vdd_1v0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc3v3_pmu: LDO_REG4 {
regulator-name = "vcc3v3_pmu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_sd: LDO_REG6 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_bl: LDO_REG7 {
regulator-name = "vcc_bl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_lcd: LDO_REG8 {
regulator-name = "vcc_lcd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <2800000>;
};
};
vcc_cam: LDO_REG9 {
regulator-name = "vcc_cam";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
};
battery {
compatible = "rk817,battery";
ocv_table = <3500 3625 3685 3697 3718 3735 3748
3760 3774 3788 3802 3816 3834 3853
3877 3908 3946 3975 4018 4071 4106>;
/* KPL605475 Battery Spec */
/*
Capacity : 3.7V 3000mA
Normal Voltage = 3.7V
Cut-Off Voltage : 3.1V
Internal Impedance : 180 mOhm
Charging Voltage : 4.2V
Charging Voltage Max : 4.25V
Sample resister : 10 mohm
*/
design_capacity = <3000>;
design_qmax = <3000>;
bat_res = <180>;
sleep_enter_current = <300>;
sleep_exit_current = <300>;
sleep_filter_current = <100>;
power_off_thresd = <3500>;
zero_algorithm_vol = <3700>;
max_soc_offset = <60>;
monitor_sec = <5>;
virtual_power = <0>;
sample_res = <10>;
};
charger {
compatible = "rk817,charger";
min_input_voltage = <4500>;
max_input_current = <1500>;
max_chrg_current = <2000>;
max_chrg_voltage = <4200>;
chrg_term_mode = <0>;
chrg_finish_cur = <300>;
virtual_power = <0>;
sample_res = <10>;
/* P.C.B rev0.2 DC Detect & Charger Status LED GPIO */
dc_det_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
chg_led_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
extcon = <&u2phy>;
};
rk817_codec: codec {
#sound-dai-cells = <0>;
compatible = "rockchip,rk817-codec";
clocks = <&cru SCLK_I2S1_OUT>;
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_mclk>;
hp-volume = <20>;
spk-volume = <3>;
status = "okay";
};
};
};
/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
&i2c1 {
clock-frequency = <400000>;
status = "okay";
};
/* I2S 1 Channel Used */
&i2s1_2ch {
status = "okay";
};
&io_domains {
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_3v3>;
vccio4-supply = <&vcc_3v3>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_3v3>;
status = "okay";
};
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
card-detect-delay = <200>;
cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&tsadc {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "disabled";
};
};
&usb20_otg {
status = "okay";
};
/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
status = "okay";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&pinctrl {
btns {
btn_pins: btn-pins {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
leds {
blue_led_pin: blue-led-pin {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
dc_det: dc-det {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
pmic_int: pmic-int {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_slppin_gpio: soc_slppin_gpio {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
};
soc_slppin_rst: soc_slppin_rst {
rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
};
soc_slppin_slp: soc_slppin_slp {
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
};
};
};

15
arch/arm/dts/rk3326.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include "px30.dtsi"
&display_subsystem {
ports = <&vopb_out>;
};
/delete-node/ &dsi_in_vopl;
/delete-node/ &lvds_vopl_in;
/delete-node/ &vopl;
/delete-node/ &vopl_mmu;

6
arch/arm/dts/rk3328-rock64-u-boot.dtsi
View file

@ -46,3 +46,9 @@
&vcc_sd {
u-boot,dm-spl;
};
&spi0 {
spi_flash: spiflash@0 {
u-boot,dm-pre-reloc;
};
};

5
arch/arm/dts/rk3328-u-boot.dtsi
View file

@ -7,6 +7,7 @@
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
spi0 = &spi0;
};
chosen {
@ -66,3 +67,7 @@
&usb20_otg {
hnp-srp-disable;
};
&spi0 {
u-boot,dm-pre-reloc;
};

26
arch/arm/dts/rk3399-rock-pi-4.dts → arch/arm/dts/rk3399-rock-pi-4.dtsi
View file

@ -11,9 +11,6 @@
#include "rk3399-opp.dtsi"
/ {
model = "Radxa ROCK Pi 4";
compatible = "radxa,rockpi4", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
@ -587,17 +584,6 @@
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
@ -666,18 +652,6 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};
&uart2 {

13
arch/arm/dts/rk3399-rock-pi-4a.dts Normal file
View file

@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
/ {
model = "Radxa ROCK Pi 4A";
compatible = "radxa,rockpi4", "rockchip,rk3399";
};

6
arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"

42
arch/arm/dts/rk3399-rock-pi-4b.dts Normal file
View file

@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
/ {
model = "Radxa ROCK Pi 4B";
compatible = "radxa,rockpi4", "rockchip,rk3399";
};
&sdio0 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};

6
arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"

51
arch/arm/dts/rk3399-rock-pi-4c.dts Normal file
View file

@ -0,0 +1,51 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2019 Radxa Limited
* Copyright (c) 2019 Amarula Solutions(India)
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
/ {
model = "Radxa ROCK Pi 4C";
compatible = "radxa,rockpi4", "rockchip,rk3399";
};
&sdio0 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};
&vcc5v0_host {
gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
};
&vcc5v0_host_en {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};

6
arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
View file

@ -5,3 +5,9 @@
#include "rk3399pro-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};

6
arch/arm/dts/rk3399pro-rock-pi-n10.dts
View file

@ -8,11 +8,15 @@
/dts-v1/;
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
#include "rk3399pro-vmarc-som.dtsi"
#include <rockchip-radxa-dalang-carrier.dtsi>
#include "rk3399pro-vmarc-som.dtsi"
/ {
model = "Radxa ROCK Pi N10";
compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som",
"rockchip,rk3399pro";
chosen {
stdout-path = "serial2:1500000n8";
};
};

205
arch/arm/dts/rk3399pro-vmarc-som.dtsi
View file

@ -12,30 +12,16 @@
/ {
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
vcc3v3_pcie: vcc-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
enable-active-high;
gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
vin-supply = <&vcc5v0_sys>;
};
};
@ -61,23 +47,20 @@
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <180>;
i2c-scl-falling-time-ns = <30>;
i2c-scl-rising-time-ns = <180>;
status = "okay";
rk809: pmic@20 {
@ -171,7 +154,8 @@
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
@ -206,7 +190,8 @@
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-on-in-suspend;
regulator-suspend-microvolt = <1850000>;
};
};
@ -297,11 +282,88 @@
};
};
&i2c1 {
i2c-scl-falling-time-ns = <30>;
i2c-scl-rising-time-ns = <140>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio4>;
interrupts = <RK_PD6 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcca_1v8>;
sdmmc-supply = <&vccio_sd>;
gpio1830-supply = <&vccio_3v0>;
sdmmc-supply = <&vccio_sd>;
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */
vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>;
};
};
pcie {
pcie_pwr: pcie-pwr {
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
};
};
vbus_host {
usb1_en_oc: usb1-en-oc {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
vbus_typec {
usb0_en_oc: usb0-en-oc {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
@ -322,17 +384,74 @@
max-frequency = <150000000>;
};
&tsadc {
&tcphy0 {
status = "okay";
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC2 0 &pcfg_pull_up>;
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
phy-supply = <&vbus_typec>;
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vbus_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_host: host-port {
phy-supply = <&vbus_host>;
status = "okay";
};
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
};
&vbus_host {
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
pinctrl-names = "default";
pinctrl-0 = <&usb1_en_oc>;
};
&vbus_typec {
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
pinctrl-names = "default";
pinctrl-0 = <&usb0_en_oc>;
};

95
arch/arm/dts/rockchip-radxa-dalang-carrier.dtsi
View file

@ -8,36 +8,66 @@
#include <dt-bindings/pwm/pwm.h>
/ {
chosen {
stdout-path = "serial2:1500000n8";
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vbus_host: vbus-host {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&usb1_en_oc>;
regulator-name = "vbus_host"; /* HOST-5V */
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vbus_typec: vbus-typec {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&usb0_en_oc>;
regulator-name = "vbus_typec";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
};
&gmac {
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&i2c1 {
&hdmi {
status = "okay";
i2c-scl-rising-time-ns = <140>;
i2c-scl-falling-time-ns = <30>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio4>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
};
};
&pwm0 {
@ -69,11 +99,18 @@
status = "okay";
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins =
<4 RK_PD6 0 &pcfg_pull_up>;
};
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

49
arch/arm/include/asm/arch-rockchip/cpu_rk3288.h Normal file
View file

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Rockchip Electronics Co., Ltd.
*/
#ifndef __ASM_ARCH_CPU_RK3288_H
#define __ASM_ARCH_CPU_RK3288_H
#include <asm/io.h>
#define ROCKCHIP_CPU_MASK 0xffff0000
#define ROCKCHIP_CPU_RK3288 0x32880000
#define ROCKCHIP_SOC_MASK (ROCKCHIP_CPU_MASK | 0xff)
#define ROCKCHIP_SOC_RK3288 (ROCKCHIP_CPU_RK3288 | 0x00)
#define ROCKCHIP_SOC_RK3288W (ROCKCHIP_CPU_RK3288 | 0x01)
#define RK3288_HDMI_PHYS 0xff980000
#define HDMI_CONFIG0_ID 0x4
#define RK3288W_HDMI_REVID 0x1a
static inline int rockchip_soc_id(void)
{
u8 reg;
#if defined(CONFIG_ROCKCHIP_RK3288)
reg = readb(RK3288_HDMI_PHYS + HDMI_CONFIG0_ID);
if (reg == RK3288W_HDMI_REVID)
return ROCKCHIP_SOC_RK3288W;
else
return ROCKCHIP_SOC_RK3288;
#else
return 0;
#endif
}
#define ROCKCHIP_SOC(id, ID) \
static inline bool soc_is_##id(void) \
{ \
int soc_id = rockchip_soc_id(); \
if (soc_id) \
return ((soc_id & ROCKCHIP_SOC_MASK) == ROCKCHIP_SOC_ ##ID); \
return false; \
}
ROCKCHIP_SOC(rk3288, RK3288)
ROCKCHIP_SOC(rk3288w, RK3288W)
#endif /* __ASM_ARCH_CPU_RK3288_H */

3
arch/arm/include/asm/arch-rockchip/cru.h
View file

@ -26,9 +26,10 @@ enum {
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
GLB_RST_ST_MASK = GENMASK(5, 0),
};
#define MHz 1000000
char *get_reset_cause(void);
#endif /* _ROCKCHIP_CLOCK_H */

15
arch/arm/include/asm/arch-rockchip/sdram_common.h
View file

@ -114,25 +114,10 @@ struct sdram_base_params {
#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch)))
#define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3))
#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
}
inline void sdram_print_stride(unsigned int stride)
{
}
#else
void sdram_print_dram_type(unsigned char dramtype);
void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base);
void sdram_print_stride(unsigned int stride);
#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
void sdram_org_config(struct sdram_cap_info *cap_info,
struct sdram_base_params *base,

1
arch/arm/mach-rockchip/Kconfig
View file

@ -99,6 +99,7 @@ config ROCKCHIP_RK322X
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
select OF_BOARD_SETUP
select SUPPORT_SPL
select SPL
select SUPPORT_TPL

5
arch/arm/mach-rockchip/Makefile
View file

@ -22,11 +22,14 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
obj-y += boot_mode.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
ifeq ($(CONFIG_TPL_BUILD),)
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/

28
arch/arm/mach-rockchip/cpu-info.c
View file

@ -13,7 +13,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <linux/err.h>
static char *get_reset_cause(void)
char *get_reset_cause(void)
{
struct rockchip_cru *cru = rockchip_get_cru();
char *cause = NULL;
@ -41,27 +41,25 @@ static char *get_reset_cause(void)
cause = "unknown reset";
}
return cause;
}
#if CONFIG_IS_ENABLED(DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
char *cause = get_reset_cause();
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
printf("Reset cause: %s\n", cause);
/**
* reset_reason env is used by rk3288, due to special use case
* to figure it the boot behavior. so keep this as it is.
*/
env_set("reset_reason", cause);
/*
* Clear glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
return cause;
}
int print_cpuinfo(void)
{
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */
return 0;
}
#endif

4
arch/arm/mach-rockchip/px30/Kconfig
View file

@ -3,6 +3,9 @@ if ROCKCHIP_PX30
config TARGET_EVB_PX30
bool "EVB_PX30"
config TARGET_ODROID_GO2
bool "ODROID_GO2"
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
@ -36,6 +39,7 @@ config DEBUG_UART_CHANNEL
For using the UART for early debugging the route to use needs
to be declared (0 or 1).
source "board/hardkernel/odroid_go2/Kconfig"
source "board/rockchip/evb_px30/Kconfig"
endif

30
arch/arm/mach-rockchip/rk3288/rk3288.c
View file

@ -13,6 +13,7 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cpu_rk3288.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
@ -115,6 +116,35 @@ int rk_board_late_init(void)
return rk3288_board_late_init();
}
static int ft_rk3288w_setup(void *blob)
{
const char *path;
int offs, ret;
path = "/clock-controller@ff760000";
offs = fdt_path_offset(blob, path);
if (offs < 0) {
debug("failed to found fdt path %s\n", path);
return offs;
}
ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru");
if (ret) {
printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret);
return ret;
}
return ret;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
if (soc_is_rk3288w())
return ft_rk3288w_setup(blob);
return 0;
}
static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{

6
arch/arm/mach-rockchip/rk3399/rk3399.c
View file

@ -241,8 +241,14 @@ static void rk3399_force_power_on_reset(void)
}
#endif
void __weak led_setup(void)
{
}
void spl_board_init(void)
{
led_setup();
#if defined(SPL_GPIO_SUPPORT)
struct rockchip_cru *cru = rockchip_get_cru();

6
arch/arm/mach-rockchip/sdram.c
View file

@ -56,16 +56,14 @@ int dram_init_banksize(void)
- CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
tos_parameter->tee_mem.size;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ top - gd->bd->bi_dram[1].start;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
} else {
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x8400000;
/* Reserve 32M for OPTEE with TA */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+ gd->bd->bi_dram[0].size + 0x2000000;
gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+ top - gd->bd->bi_dram[1].start;
gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
}
#else
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;

7
arch/arm/mach-rockchip/tpl.c
View file

@ -43,18 +43,11 @@ __weak void rockchip_stimer_init(void)
TIMER_CONTROL_REG);
}
__weak int board_early_init_f(void)
{
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
board_early_init_f();
#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT)
/*
* Debug UART can be used from here if required:

48
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
View file

@ -5,12 +5,15 @@
#include <common.h>
#include <dm.h>
#include <env.h>
#include <log.h>
#include <asm/arch-rockchip/periph.h>
#include <power/regulator.h>
#include <spl_gpio.h>
#include <asm/io.h>
#include <power/regulator.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
@ -30,19 +33,46 @@ int board_early_init_f(void)
out:
return 0;
}
#endif
#if defined(CONFIG_TPL_BUILD)
#else
#define GPIO0_BASE 0xff720000
#define PMUGRF_BASE 0xff320000
#define GPIO0_BASE 0xff720000
int board_early_init_f(void)
/**
* LED setup for roc-rk3399-pc
*
* 1. Set the low power leds (only during POR, pwr_key env is 'y')
* glow yellow LED, termed as low power
* poll for on board power key press
* once powe key pressed, turn off yellow
* 2. Turn on red LED, indicating full power mode
*/
void led_setup(void)
{
struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
bool press_pwr_key = false;
if (IS_ENABLED(CONFIG_SPL_ENV_SUPPORT)) {
env_init();
env_load();
if (env_get_yesno("pwr_key") == 1)
press_pwr_key = true;
}
if (press_pwr_key && !strcmp(get_reset_cause(), "POR")) {
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5),
GPIO_PULL_NORMAL);
while (readl(&gpio0->ext_port) & 0x20)
;
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
}
/* Turn on red LED, indicating full power mode */
spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
return 0;
}
#endif

15
board/hardkernel/odroid_go2/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_ODROID_GO2
config SYS_BOARD
default "odroid_go2"
config SYS_VENDOR
default "hardkernel"
config SYS_CONFIG_NAME
default "odroid_go2"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/hardkernel/odroid_go2/MAINTAINERS Normal file
View file

@ -0,0 +1,6 @@
GO2
M: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
S: Maintained
F: board/odroid/go2
F: include/configs/odroid_go2.h
F: configs/odroid-go2_defconfig

7
board/hardkernel/odroid_go2/Makefile Normal file
View file

@ -0,0 +1,7 @@
#
# Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += go2.o

4
board/hardkernel/odroid_go2/go2.c Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/

2
board/rockchip/evb_rk3399/MAINTAINERS
View file

@ -68,6 +68,8 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-4-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
F: configs/rock-pi-4c-rk3399_defconfig
F: arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
ROCK-PI-N10
M: Jagan Teki <jagan@amarulasolutions.com>

4
configs/firefly-rk3399_defconfig
View file

@ -8,6 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -23,7 +24,6 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@ -54,6 +54,8 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y

119
configs/odroid-go2_defconfig Normal file
View file

@ -0,0 +1,119 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4000
CONFIG_ROCKCHIP_PX30=y
CONFIG_TARGET_ODROID_GO2=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF160000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_CHANNEL=1
CONFIG_SPL_TEXT_BASE=0x00000000
CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_FDT_FILE="rk3326-odroidgo2.dtb"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_SETEXPR=y
# CONFIG_CMD_MISC is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_DEFAULT_DEVICE_TREE="rk3326-odroid-go2"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
# CONFIG_TPL_DM_SERIAL is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_SOUND=y
CONFIG_SYSRESET=y
CONFIG_OPTEE=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_LCD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_LZ4=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set

14
configs/roc-pc-mezzanine-rk3399_defconfig
View file

@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
@ -13,14 +14,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -33,6 +35,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@ -52,6 +55,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
@ -65,7 +69,9 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y

14
configs/roc-pc-rk3399_defconfig
View file

@ -1,8 +1,9 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_SIZE=0x6000
CONFIG_ENV_OFFSET=0x460000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_DM_SPI=y
CONFIG_ROCKCHIP_RK3399=y
@ -13,14 +14,15 @@ CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_TPL=y
CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
@ -32,6 +34,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
@ -49,6 +52,7 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
@ -62,7 +66,9 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y

20
configs/rock-pi-4-rk3399_defconfig
View file

@ -8,7 +8,8 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4b.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
@ -18,16 +19,18 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4"
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4b"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
@ -35,11 +38,16 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
@ -48,11 +56,19 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

74
configs/rock-pi-4c-rk3399_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y

25
configs/rock-pi-n10-rk3399pro_defconfig
View file

@ -9,6 +9,8 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
@ -19,6 +21,8 @@ CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
@ -36,11 +40,32 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
# CONFIG_USB_KEYBOARD_FN_KEYS is not set
CONFIG_USB_GADGET=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_ERRNO_STR=y

17
configs/rock-pi-n8-rk3288_defconfig
View file

@ -11,8 +11,10 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_DEFAULT_FDT_FILE="rk3288-rock-pi-n8.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
@ -22,6 +24,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@ -61,6 +64,20 @@ CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
# CONFIG_USB_KEYBOARD_FN_KEYS is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_ERRNO_STR=y

2
configs/rock64-rk3328_defconfig
View file

@ -97,3 +97,5 @@ CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SMBIOS_MANUFACTURER="pine64"
CONFIG_ROCKCHIP_SPI=y
CONFIG_SPI_FLASH_GIGADEVICE=y

4
configs/rockpro64-rk3399_defconfig
View file

@ -49,6 +49,8 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
@ -66,6 +68,8 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

31
drivers/clk/rockchip/clk_rk3328.c
View file

@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
return rk3328_saradc_get_clk(cru);
}
static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
{
u32 div, val;
val = readl(&cru->clksel_con[24]);
div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
return DIV_TO_RATE(OSC_HZ, div);
}
static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
{
u32 src_clk_div;
src_clk_div = GPLL_HZ / hz;
assert(src_clk_div < 128);
rk_clrsetreg(&cru->clksel_con[24],
CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
(src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
return rk3328_spi_get_clk(cru);
}
static ulong rk3328_clk_get_rate(struct clk *clk)
{
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
case SCLK_SARADC:
rate = rk3328_saradc_get_clk(priv->cru);
break;
case SCLK_SPI:
rate = rk3328_spi_get_clk(priv->cru);
break;
default:
return -ENOENT;
}
@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SARADC:
ret = rk3328_saradc_set_clk(priv->cru, rate);
break;
case SCLK_SPI:
ret = rk3328_spi_set_clk(priv->cru, rate);
break;
case DCLK_LCDC:
case SCLK_PDM:
case SCLK_RTC32K:

1
drivers/pci/Kconfig
View file

@ -200,6 +200,7 @@ config PCIE_MEDIATEK
config PCIE_ROCKCHIP
bool "Enable Rockchip PCIe driver"
select DM_PCI
select PHY_ROCKCHIP_PCIE
default y if ROCKCHIP_RK3399
help
Say Y here if you want to enable PCIe controller support on

2
drivers/pci/Makefile
View file

@ -43,5 +43,5 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o
obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o

95
drivers/pci/pcie_rockchip.c
View file

@ -15,6 +15,7 @@
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
#include <pci.h>
#include <power-domain.h>
#include <power/regulator.h>
@ -25,10 +26,80 @@
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
#include "pcie_rockchip.h"
DECLARE_GLOBAL_DATA_PTR;
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
#define PCIE_CLIENT_BASE 0x0
#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
#define PCIE_CLIENT_BASIC_STATUS1 0x0048
#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
#define PCIE_LINK_UP(x) \
(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
#define PCIE_RC_NORMAL_BASE 0x800000
#define PCIE_LM_BASE 0x900000
#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
#define PCIE_LM_RCBARPIE BIT(19)
#define PCIE_LM_RCBARPIS BIT(20)
#define PCIE_RC_BASE 0xa00000
#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
#define PCIE_ATR_BASE 0xc00000
#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
#define PCIE_ATR_HDR_MEM 0x2
#define PCIE_ATR_HDR_IO 0x6
#define PCIE_ATR_HDR_CFG_TYPE0 0xa
#define PCIE_ATR_HDR_CFG_TYPE1 0xb
#define PCIE_ATR_HDR_RID BIT(23)
#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
struct rockchip_pcie {
fdt_addr_t axi_base;
fdt_addr_t apb_base;
int first_busno;
struct udevice *dev;
/* resets */
struct reset_ctl core_rst;
struct reset_ctl mgmt_rst;
struct reset_ctl mgmt_sticky_rst;
struct reset_ctl pipe_rst;
struct reset_ctl pm_rst;
struct reset_ctl pclk_rst;
struct reset_ctl aclk_rst;
/* gpio */
struct gpio_desc ep_gpio;
/* vpcie regulators */
struct udevice *vpcie12v;
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
/* phy */
struct phy pcie_phy;
};
static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset)
{
unsigned int bus = PCI_BUS(bdf);
@ -159,8 +230,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
static int rockchip_pcie_init_port(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
struct rockchip_pcie_phy *phy = pcie_get_phy(priv);
struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy);
u32 cr, val, status;
int ret;
@ -185,7 +254,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return ret;
}
ret = ops->init(phy);
ret = generic_phy_init(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to init phy (ret=%d)\n", ret);
goto err_exit_phy;
@ -242,7 +311,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
ret = ops->power_on(phy);
ret = generic_phy_power_on(&priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
goto err_power_off_phy;
@ -311,9 +380,9 @@ static int rockchip_pcie_init_port(struct udevice *dev)
return 0;
err_power_off_phy:
ops->power_off(phy);
generic_phy_power_off(&priv->pcie_phy);
err_exit_phy:
ops->exit(phy);
generic_phy_exit(&priv->pcie_phy);
return ret;
}
@ -443,6 +512,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
return ret;
}
ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
if (ret) {
dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
return ret;
}
return 0;
}
@ -460,10 +535,6 @@ static int rockchip_pcie_probe(struct udevice *dev)
if (ret)
return ret;
ret = rockchip_pcie_phy_get(dev);
if (ret)
return ret;
ret = rockchip_pcie_set_vpcie(dev);
if (ret)
return ret;

141
drivers/pci/pcie_rockchip.h
View file

@ -1,141 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Rockchip PCIe Headers
*
* Copyright (c) 2016 Rockchip, Inc.
* Copyright (c) 2020 Amarula Solutions(India)
* Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
* Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
*
*/
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
#define PCIE_CLIENT_BASE 0x0
#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
#define PCIE_CLIENT_BASIC_STATUS1 0x0048
#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
#define PCIE_LINK_UP(x) \
(((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
#define PCIE_RC_NORMAL_BASE 0x800000
#define PCIE_LM_BASE 0x900000
#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
#define PCIE_LM_RCBARPIE BIT(19)
#define PCIE_LM_RCBARPIS BIT(20)
#define PCIE_RC_BASE 0xa00000
#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
#define PCIE_ATR_BASE 0xc00000
#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
#define PCIE_ATR_HDR_MEM 0x2
#define PCIE_ATR_HDR_IO 0x6
#define PCIE_ATR_HDR_CFG_TYPE0 0xa
#define PCIE_ATR_HDR_CFG_TYPE1 0xb
#define PCIE_ATR_HDR_RID BIT(23)
#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
/*
* The higher 16-bit of this register is used for write protection
* only if BIT(x + 16) set to 1 the BIT(x) can be written.
*/
#define HIWORD_UPDATE_MASK(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
#define PHY_CFG_DATA_SHIFT 7
#define PHY_CFG_ADDR_SHIFT 1
#define PHY_CFG_DATA_MASK 0xf
#define PHY_CFG_ADDR_MASK 0x3f
#define PHY_CFG_RD_MASK 0x3ff
#define PHY_CFG_WR_ENABLE 1
#define PHY_CFG_WR_DISABLE 1
#define PHY_CFG_WR_SHIFT 0
#define PHY_CFG_WR_MASK 1
#define PHY_CFG_PLL_LOCK 0x10
#define PHY_CFG_CLK_TEST 0x10
#define PHY_CFG_CLK_SCC 0x12
#define PHY_CFG_SEPE_RATE BIT(3)
#define PHY_CFG_PLL_100M BIT(3)
#define PHY_PLL_LOCKED BIT(9)
#define PHY_PLL_OUTPUT BIT(10)
#define PHY_LANE_IDLE_OFF 0x1
#define PHY_LANE_IDLE_MASK 0x1
#define PHY_LANE_IDLE_A_SHIFT 3
#define PHY_LANE_IDLE_B_SHIFT 4
#define PHY_LANE_IDLE_C_SHIFT 5
#define PHY_LANE_IDLE_D_SHIFT 6
#define PCIE_PHY_CONF 0xe220
#define PCIE_PHY_STATUS 0xe2a4
#define PCIE_PHY_LANEOFF 0xe214
struct rockchip_pcie_phy {
void *reg_base;
struct clk refclk;
struct reset_ctl phy_rst;
struct rockchip_pcie_phy_ops *ops;
};
struct rockchip_pcie_phy_ops {
int (*init)(struct rockchip_pcie_phy *phy);
int (*exit)(struct rockchip_pcie_phy *phy);
int (*power_on)(struct rockchip_pcie_phy *phy);
int (*power_off)(struct rockchip_pcie_phy *phy);
};
struct rockchip_pcie {
fdt_addr_t axi_base;
fdt_addr_t apb_base;
int first_busno;
struct udevice *dev;
struct rockchip_pcie_phy rk_phy;
struct rockchip_pcie_phy *phy;
/* resets */
struct reset_ctl core_rst;
struct reset_ctl mgmt_rst;
struct reset_ctl mgmt_sticky_rst;
struct reset_ctl pipe_rst;
struct reset_ctl pm_rst;
struct reset_ctl pclk_rst;
struct reset_ctl aclk_rst;
/* gpio */
struct gpio_desc ep_gpio;
/* vpcie regulators */
struct udevice *vpcie12v;
struct udevice *vpcie3v3;
struct udevice *vpcie1v8;
struct udevice *vpcie0v9;
};
int rockchip_pcie_phy_get(struct udevice *dev);
static inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie)
{
return pcie->phy;
}
static inline struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy)
{
return (struct rockchip_pcie_phy_ops *)phy->ops;
}

205
drivers/pci/pcie_rockchip_phy.c
View file

@ -1,205 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Rockchip PCIe PHY driver
*
* Copyright (c) 2016 Rockchip, Inc.
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <reset.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/iopoll.h>
#include <asm/arch-rockchip/clock.h>
#include "pcie_rockchip.h"
DECLARE_GLOBAL_DATA_PTR;
static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data)
{
u32 reg;
reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_CONF);
udelay(1);
reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE,
PHY_CFG_WR_MASK,
PHY_CFG_WR_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_CONF);
udelay(1);
reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE,
PHY_CFG_WR_MASK,
PHY_CFG_WR_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_CONF);
}
static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy)
{
int ret = 0;
u32 reg, status;
ret = reset_deassert(&phy->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
return ret;
}
reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_CONF);
reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
ret = -EINVAL;
ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
status,
status & PHY_PLL_LOCKED,
20 * 1000,
50);
if (ret) {
dev_err(&phy->dev, "pll lock timeout!\n");
goto err_pll_lock;
}
phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
ret = -ETIMEDOUT;
ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
status,
!(status & PHY_PLL_OUTPUT),
20 * 1000,
50);
if (ret) {
dev_err(&phy->dev, "pll output enable timeout!\n");
goto err_pll_lock;
}
reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK,
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_CONF);
ret = -EINVAL;
ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS,
status,
status & PHY_PLL_LOCKED,
20 * 1000,
50);
if (ret) {
dev_err(&phy->dev, "pll relock timeout!\n");
goto err_pll_lock;
}
return 0;
err_pll_lock:
reset_assert(&phy->phy_rst);
return ret;
}
static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy)
{
int ret;
u32 reg;
reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT);
writel(reg, phy->reg_base + PCIE_PHY_LANEOFF);
ret = reset_assert(&phy->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
return ret;
}
return 0;
}
static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy)
{
int ret;
ret = clk_enable(&phy->refclk);
if (ret) {
dev_err(dev, "failed to enable refclk clock\n");
return ret;
}
ret = reset_assert(&phy->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
goto err_reset;
}
return 0;
err_reset:
clk_disable(&phy->refclk);
return ret;
}
static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy)
{
clk_disable(&phy->refclk);
return 0;
}
static struct rockchip_pcie_phy_ops pcie_phy_ops = {
.init = rockchip_pcie_phy_init,
.power_on = rockchip_pcie_phy_power_on,
.power_off = rockchip_pcie_phy_power_off,
.exit = rockchip_pcie_phy_exit,
};
int rockchip_pcie_phy_get(struct udevice *dev)
{
struct rockchip_pcie *priv = dev_get_priv(dev);
struct rockchip_pcie_phy *phy_priv = &priv->rk_phy;
ofnode phy_node;
u32 phandle;
int ret;
phandle = dev_read_u32_default(dev, "phys", 0);
phy_node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(phy_node)) {
dev_err(dev, "failed to found pcie-phy\n");
return -ENODEV;
}
phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk);
if (ret) {
dev_err(dev, "failed to get refclk clock phandle\n");
return ret;
}
ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst);
if (ret) {
dev_err(dev, "failed to get phy reset phandle\n");
return ret;
}
phy_priv->ops = &pcie_phy_ops;
priv->phy = phy_priv;
return 0;
}

7
drivers/phy/rockchip/Kconfig
View file

@ -11,6 +11,13 @@ config PHY_ROCKCHIP_INNO_USB2
help
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
config PHY_ROCKCHIP_PCIE
bool "Rockchip PCIe PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
Enable this to support the Rockchip PCIe PHY.
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
depends on ARCH_ROCKCHIP

1
drivers/phy/rockchip/Makefile
View file

@ -4,4 +4,5 @@
#
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o

271
drivers/phy/rockchip/phy-rockchip-pcie.c Normal file
View file

@ -0,0 +1,271 @@
// SPDX-License-Identifier: (GPL-2.0-only)
/*
* Rockchip PCIe PHY driver
*
* Copyright (C) 2020 Amarula Solutions(India)
* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
* Copyright (C) 2016 ROCKCHIP, Inc.
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <generic-phy.h>
#include <reset.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/iopoll.h>
#include <asm/arch-rockchip/clock.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The higher 16-bit of this register is used for write protection
* only if BIT(x + 16) set to 1 the BIT(x) can be written.
*/
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
#define PHY_MAX_LANE_NUM 4
#define PHY_CFG_DATA_SHIFT 7
#define PHY_CFG_ADDR_SHIFT 1
#define PHY_CFG_DATA_MASK 0xf
#define PHY_CFG_ADDR_MASK 0x3f
#define PHY_CFG_RD_MASK 0x3ff
#define PHY_CFG_WR_ENABLE 1
#define PHY_CFG_WR_DISABLE 1
#define PHY_CFG_WR_SHIFT 0
#define PHY_CFG_WR_MASK 1
#define PHY_CFG_PLL_LOCK 0x10
#define PHY_CFG_CLK_TEST 0x10
#define PHY_CFG_CLK_SCC 0x12
#define PHY_CFG_SEPE_RATE BIT(3)
#define PHY_CFG_PLL_100M BIT(3)
#define PHY_PLL_LOCKED BIT(9)
#define PHY_PLL_OUTPUT BIT(10)
#define PHY_LANE_RX_DET_SHIFT 11
#define PHY_LANE_RX_DET_TH 0x1
#define PHY_LANE_IDLE_OFF 0x1
#define PHY_LANE_IDLE_MASK 0x1
#define PHY_LANE_IDLE_A_SHIFT 3
#define PHY_LANE_IDLE_B_SHIFT 4
#define PHY_LANE_IDLE_C_SHIFT 5
#define PHY_LANE_IDLE_D_SHIFT 6
struct rockchip_pcie_phy_data {
unsigned int pcie_conf;
unsigned int pcie_status;
unsigned int pcie_laneoff;
};
struct rockchip_pcie_phy {
void *reg_base;
struct clk refclk;
struct reset_ctl phy_rst;
const struct rockchip_pcie_phy_data *data;
};
static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
{
u32 reg;
reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_conf);
udelay(1);
reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
PHY_CFG_WR_MASK,
PHY_CFG_WR_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_conf);
udelay(1);
reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
PHY_CFG_WR_MASK,
PHY_CFG_WR_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_conf);
}
static int rockchip_pcie_phy_power_on(struct phy *phy)
{
struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
int ret = 0;
u32 reg, status;
ret = reset_deassert(&priv->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
return ret;
}
reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_conf);
reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_laneoff);
ret = -EINVAL;
ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
status,
status & PHY_PLL_LOCKED,
20 * 1000,
50);
if (ret) {
dev_err(&priv->dev, "pll lock timeout!\n");
goto err_pll_lock;
}
phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
ret = -ETIMEDOUT;
ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
status,
!(status & PHY_PLL_OUTPUT),
20 * 1000,
50);
if (ret) {
dev_err(&priv->dev, "pll output enable timeout!\n");
goto err_pll_lock;
}
reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_conf);
ret = -EINVAL;
ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
status,
status & PHY_PLL_LOCKED,
20 * 1000,
50);
if (ret) {
dev_err(&priv->dev, "pll relock timeout!\n");
goto err_pll_lock;
}
return 0;
err_pll_lock:
reset_assert(&priv->phy_rst);
return ret;
}
static int rockchip_pcie_phy_power_off(struct phy *phy)
{
struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
int ret;
u32 reg;
reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT);
writel(reg, priv->reg_base + priv->data->pcie_laneoff);
ret = reset_assert(&priv->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
return ret;
}
return 0;
}
static int rockchip_pcie_phy_init(struct phy *phy)
{
struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
int ret;
ret = clk_enable(&priv->refclk);
if (ret) {
dev_err(dev, "failed to enable refclk clock\n");
return ret;
}
ret = reset_assert(&priv->phy_rst);
if (ret) {
dev_err(dev, "failed to assert phy reset\n");
goto err_reset;
}
return 0;
err_reset:
clk_disable(&priv->refclk);
return ret;
}
static int rockchip_pcie_phy_exit(struct phy *phy)
{
struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
clk_disable(&priv->refclk);
return 0;
}
static struct phy_ops rockchip_pcie_phy_ops = {
.init = rockchip_pcie_phy_init,
.power_on = rockchip_pcie_phy_power_on,
.power_off = rockchip_pcie_phy_power_off,
.exit = rockchip_pcie_phy_exit,
};
static int rockchip_pcie_phy_probe(struct udevice *dev)
{
struct rockchip_pcie_phy *priv = dev_get_priv(dev);
int ret;
priv->data = (const struct rockchip_pcie_phy_data *)
dev_get_driver_data(dev);
if (!priv->data)
return -EINVAL;
priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
ret = clk_get_by_name(dev, "refclk", &priv->refclk);
if (ret) {
dev_err(dev, "failed to get refclk clock phandle\n");
return ret;
}
ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
if (ret) {
dev_err(dev, "failed to get phy reset phandle\n");
return ret;
}
return 0;
}
static const struct rockchip_pcie_phy_data rk3399_pcie_data = {
.pcie_conf = 0xe220,
.pcie_status = 0xe2a4,
.pcie_laneoff = 0xe214,
};
static const struct udevice_id rockchip_pcie_phy_ids[] = {
{
.compatible = "rockchip,rk3399-pcie-phy",
.data = (ulong)&rk3399_pcie_data,
},
{ /* sentile */ }
};
U_BOOT_DRIVER(rockchip_pcie_phy) = {
.name = "rockchip_pcie_phy",
.id = UCLASS_PHY,
.of_match = rockchip_pcie_phy_ids,
.ops = &rockchip_pcie_phy_ops,
.probe = rockchip_pcie_phy_probe,
.priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
};

13
drivers/ram/rockchip/sdram_common.c
View file

@ -117,6 +117,19 @@ void sdram_print_stride(unsigned int stride)
printf("no stride\n");
}
}
#else
inline void sdram_print_dram_type(unsigned char dramtype)
{
}
inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
struct sdram_base_params *base)
{
}
inline void sdram_print_stride(unsigned int stride)
{
}
#endif
/*

37
drivers/ram/rockchip/sdram_rk3399.c
View file

@ -2551,8 +2551,10 @@ static int lpddr4_set_rate(struct dram_info *dram,
lpddr4_set_ctl(dram, params, ctl_fn,
dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
printf("%s: change freq to %d mhz %d, %d\n", __func__,
dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG))
printf("%s: change freq to %d mhz %d, %d\n", __func__,
dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq,
ctl_fn, phy_fn);
}
return 0;
@ -2875,31 +2877,6 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params)
if (stride == (-1))
goto error;
}
switch (stride) {
case 0xc:
printf("128B stride\n");
break;
case 5:
case 9:
case 0xd:
case 0x11:
case 0x19:
printf("256B stride\n");
break;
case 0xa:
case 0xe:
case 0x12:
printf("512B stride\n");
break;
case 0xf:
printf("4K stride\n");
break;
case 0x1f:
printf("32MB + 256B stride\n");
break;
default:
printf("no stride\n");
}
sdram_print_stride(stride);
@ -2991,8 +2968,10 @@ static int sdram_init(struct dram_info *dram,
params->base.num_channels++;
}
printf("Channel ");
printf(channel ? "1: " : "0: ");
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
printf("Channel ");
printf(channel ? "1: " : "0: ");
}
if (channel == 0)
set_ddr_stride(dram->pmusgrf, 0x17);

2
drivers/spi/rk_spi.c
View file

@ -545,7 +545,9 @@ const struct rockchip_spi_params rk3399_spi_params = {
};
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3066-spi" },
{ .compatible = "rockchip,rk3288-spi" },
{ .compatible = "rockchip,rk3328-spi" },
{ .compatible = "rockchip,rk3368-spi",
.data = (ulong)&rk3399_spi_params },
{ .compatible = "rockchip,rk3399-spi",

6
include/configs/evb_rk3288.h
View file

@ -6,7 +6,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define ROCKCHIP_DEVICE_SETTINGS
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 0

17
include/configs/odroid_go2.h Normal file
View file

@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#ifndef __EVB_PX30_H
#define __EVB_PX30_H
#include <configs/px30_common.h>
#define CONFIG_SYS_MMC_ENV_DEV 0
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#endif

4
include/configs/rk3399_common.h
View file

@ -53,7 +53,9 @@
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
"kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x06000000\0"
"ramdisk_addr_r=0x06000000\0" \
"kernel_comp_addr_r=0x08000000\0" \
"kernel_comp_size=0x2000000\0"
#ifndef ROCKCHIP_DEVICE_SETTINGS
#define ROCKCHIP_DEVICE_SETTINGS