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Merge patch series "Kconfig: some cleanups"

Browse source 
Michal Simek <michal.simek@amd.com> says:

I looked as cleaning up some dependencies and I found that qconfig is
reporting some issues. This series is fixing some of them. But there are
still some other pending. That's why please go and fix them if they are
related to your board.

UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in
a loop you will find some other issue with copyright chars or some issues
in files taken from the Linux kernel like DTs. They should be likely fixed
in the kernel first.
Based on discussion I am ignoring names too.
This commit is contained in:
Tom Rini 2024-04-22 11:01:56 -06:00
commit 9552923ded
43 changed files with 107 additions and 107 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
View file

@ -258,7 +258,7 @@ int setup_serdes_volt(u32 svdd)
/* Wait for SVDD to stabilize */
udelay(100);
/* For each PLL that’s not disabled via RCW */
/* For each PLL that's not disabled via RCW */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {

2
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View file

@ -483,7 +483,7 @@ int setup_serdes_volt(u32 svdd)
ret = -1;
}
/* For each PLL that’s not disabled via RCW enable the SERDES */
/* For each PLL that's not disabled via RCW enable the SERDES */
#ifdef CONFIG_SYS_FSL_SRDS_1
cfg_tmp = cfg_rcwsrds1 & 0x3;
do_serdes_enable(cfg_tmp, serdes1_base);

12
arch/arm/mach-imx/ddrmc-vf610-calibration.c
View file

@ -45,7 +45,7 @@
* based on trace length differences from their
* layout.
* Mismatches up to 25% or tCK (clock period) are
* allowed, so the value in the filed doesn’t have
* allowed, so the value in the filed doesn't have
* to be very accurate.
*
* - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
@ -184,14 +184,14 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
(tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
/* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
/* Program Leveling mode - CR93[SW_LVL_MODE] to 'b10 */
clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
DDRMC_CR93_SW_LVL_MODE(0x2));
tmp = readl(&ddrmr->cr[93]);
debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
(tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
/* Start procedure - CR93[SWLVL_START] to ’b1 */
/* Start procedure - CR93[SWLVL_START] to 'b1 */
sw_leveling_start;
/* Poll CR94[SWLVL_OP_DONE] */
@ -211,7 +211,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
i << DDRMC_CR105_RDLVL_DL_0_OFF);
/* Load values CR93[SWLVL_LOAD] to ’b1 */
/* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@ -263,7 +263,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
i << DDRMC_CR110_RDLVL_DL_1_OFF);
/* Load values CR93[SWLVL_LOAD] to ’b1 */
/* Load values CR93[SWLVL_LOAD] to 'b1 */
sw_leveling_load_value;
/* Poll CR94[SWLVL_OP_DONE] */
@ -317,7 +317,7 @@ static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
sw_leveling_load_value;
sw_leveling_op_done;
/* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
/* Exit procedure - CR94[SWLVL_EXIT] to 'b1 */
sw_leveling_exit;
/* Poll CR94[SWLVL_OP_DONE] */

8
arch/arm/mach-imx/mx6/clock.c
View file

@ -714,10 +714,10 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
/*
* Register: PLL_VIDEO
* Bit Field: POST_DIV_SELECT
* 00 — Divide by 4.
* 01 — Divide by 2.
* 10 — Divide by 1.
* 11 — Reserved
* 00 - Divide by 4.
* 01 - Divide by 2.
* 10 - Divide by 1.
* 11 - Reserved
* No need to check post_div(1)
*/
for (post_div = 2; post_div <= 4; post_div <<= 1) {

4
arch/arm/mach-imx/mx7/psci-mx7.c
View file

@ -631,9 +631,9 @@ __secure void psci_system_suspend(u32 __always_unused function_id,
* Workaround:
* If both CPU0/CPU1 are IDLE, the last IDLE CPU should
* disable GIC first, then REG_BYPASS_COUNTER is used
* to mask wakeup INT, and then execute “wfi” is used to
* to mask wakeup INT, and then execute "wfi" is used to
* bring the system into power down processing safely.
* The counter must be enabled as close to the “wfi” state
* The counter must be enabled as close to the "wfi" state
* as possible. The following equation can be used to
* determine the RBC counter value:
* RBC_COUNT * (1/32K RTC frequency) >=

4
arch/arm/mach-rockchip/px30/Kconfig
View file

@ -36,9 +36,9 @@ config TARGET_PX30_CORE
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
config TARGET_RINGNECK_PX30
bool "Theobroma Systems PX30-µQ7 (Ringneck)"
bool "Theobroma Systems PX30-uQ7 (Ringneck)"
help
The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm,
The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm,
MXM-230 connector) system-on-module from Theobroma Systems[1],
featuring the Rockchip PX30.

24
arch/arm/mach-rockchip/rk3588/Kconfig
View file

@ -66,7 +66,7 @@ config TARGET_NANOPCT6_RK3588
HDMI2.0, and HDMI1.4
2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1
USB-A: USB 3.0, Type A
USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0
USB-C: Full function USB Type-C port, DP display up to 4Kp60, USB 3.0
40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs,
8x PWMs, 2x I2Ss, 28x GPIOs
Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps
@ -117,7 +117,7 @@ config TARGET_ROCK5A_RK3588
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
4-lane MIPI DSI connector
Audio – 3.5mm earphone jack
Audio - 3.5mm earphone jack
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
@ -197,7 +197,7 @@ config TARGET_TOYBRICK_RK3588
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16GB Memory LPDDR4x
Mali G610MC4 GPU
2× MIPI-CSI0 Connector
2x MIPI-CSI0 Connector
1x 2Lanes PCIe3.0 Connector
1x SATA3.0 Connector
32GB eMMC Module
@ -221,14 +221,14 @@ config ROCKCHIP_COMMON_STACK_ADDR
config TEXT_BASE
default 0x00a00000
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
source board/turing/turing-rk1-rk3588/Kconfig
source board/radxa/rock5a-rk3588s/Kconfig
source board/radxa/rock5b-rk3588/Kconfig
source board/rockchip/evb_rk3588/Kconfig
source board/rockchip/toybrick_rk3588/Kconfig
source board/theobroma-systems/jaguar_rk3588/Kconfig
source "board/edgeble/neural-compute-module-6/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/pine64/quartzpro64-rk3588/Kconfig"
source "board/turing/turing-rk1-rk3588/Kconfig"
source "board/radxa/rock5a-rk3588s/Kconfig"
source "board/radxa/rock5b-rk3588/Kconfig"
source "board/rockchip/evb_rk3588/Kconfig"
source "board/rockchip/toybrick_rk3588/Kconfig"
source "board/theobroma-systems/jaguar_rk3588/Kconfig"
endif

4
arch/arm/mach-rockchip/rv1108/Kconfig
View file

@ -36,7 +36,7 @@ config SYS_SOC
config SYS_MALLOC_F_LEN
default 0x400
source board/rockchip/evb_rv1108/Kconfig
source board/elgin/elgin_rv1108/Kconfig
source "board/rockchip/evb_rv1108/Kconfig"
source "board/elgin/elgin_rv1108/Kconfig"
endif

8
arch/arm/mach-rockchip/rv1126/Kconfig
View file

@ -6,8 +6,8 @@ config TARGET_RV1126_NEU2
Neu2:
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC.
Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC.
Neu2 powered with Consumer grade (0 to +80 deg C) RV1126 SoC.
Neu2k powered with Industrial grade (-40 C to +85 deg C) RV1126K SoC.
Neu2-IO:
Neural Compute Module 2(Neu2) IO board is an industrial form factor
@ -64,7 +64,7 @@ config SYS_MALLOC_F_LEN
config TEXT_BASE
default 0x600000
source board/edgeble/neural-compute-module-2/Kconfig
source board/itead/sonoff-ihost/Kconfig
source "board/edgeble/neural-compute-module-2/Kconfig"
source "board/itead/sonoff-ihost/Kconfig"
endif

2
arch/mips/mach-mscc/include/mach/ddr.h
View file

@ -225,7 +225,7 @@
#define VC3_MPAR_FAW VC3_MPAR_tFAW
#define VC3_MPAR_BL 4
#define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
/* ODT_RTT: “0x0040” for 120ohm, and “0x0004” for 60ohm. */
/* ODT_RTT: "0x0040" for 120ohm, and "0x0004" for 60ohm. */
#define MSCC_MEMPARM_MR1 0x0040
#define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)
#define MSCC_MEMPARM_MR3 0

2
arch/mips/mach-octeon/include/mach/cvmx-helper-pki.h
View file

@ -267,7 +267,7 @@ void cvmx_helper_pki_set_fcs_op(int node, int interface, int nports, int has_fcs
* buffer separate from the work queue entry. Words following the
* WQE in the same cache line will be zeroed, other lines in the
* buffer will not be modified and will retain stale data (from the
* buffer’s previous use). This setting may decrease the peak PKI
* buffer's previous use). This setting may decrease the peak PKI
* performance by up to half on small packets.
*/
void cvmx_helper_pki_set_wqe_mode(int node, bool pkt_outside_wqe);

6
arch/mips/mach-octeon/include/mach/cvmx-pki.h
View file

@ -110,8 +110,8 @@ enum cvmx_pki_wqe_vlan { CVMX_PKI_USE_FIRST_VLAN = 0, CVMX_PKI_USE_SECOND_VLAN }
* Controls how the PKI statistics counters are handled
* The PKI_STAT*_X registers can be indexed either by port kind (pkind), or
* final style. (Does not apply to the PKI_STAT_INB* registers.)
* 0 = X represents the packet’s pkind
* 1 = X represents the low 6-bits of packet’s final style
* 0 = X represents the packet's pkind
* 1 = X represents the low 6-bits of packet's final style
*/
enum cvmx_pki_stats_mode { CVMX_PKI_STAT_MODE_PKIND, CVMX_PKI_STAT_MODE_STYLE };
@ -880,7 +880,7 @@ int cvmx_pki_get_pkind_style(int node, int pkind);
* buffer separate from the work queue entry. Words following the
* WQE in the same cache line will be zeroed, other lines in the
* buffer will not be modified and will retain stale data (from the
* buffer’s previous use). This setting may decrease the peak PKI
* buffer's previous use). This setting may decrease the peak PKI
* performance by up to half on small packets.
*/
void cvmx_pki_set_wqe_mode(int node, u64 style, bool pkt_outside_wqe);

2
arch/mips/mach-octeon/include/mach/cvmx-pko3.h
View file

@ -366,7 +366,7 @@ enum cvmx_pko_memalg_e {
*/
MEMALG_SETRSLT = 2, /* [DSZ] = B64; mem = PKO_MEM_RESULT_S. */
MEMALG_ADD = 8, /* mem = mem + PKO_SEND_MEM_S[OFFSET] */
MEMALG_SUB = 9, /* mem = mem – PKO_SEND_MEM_S[OFFSET] */
MEMALG_SUB = 9, /* mem = mem - PKO_SEND_MEM_S[OFFSET] */
MEMALG_ADDLEN = 0xA, /* mem += [OFFSET] + PKO_SEND_HDR_S[TOTAL] */
MEMALG_SUBLEN = 0xB, /* mem -= [OFFSET] + PKO_SEND_HDR_S[TOTAL] */
MEMALG_ADDMBUF = 0xC, /* mem += [OFFSET] + mbufs_freed */

2
board/CZ.NIC/turris_mox/turris_mox.c
View file

@ -395,7 +395,7 @@ static void load_spi_dtb(void)
return;
/*
* SPI NOR "dtb" partition offset & size hardcoded for now because the
* SPI NOR "dtb" partition offset & size hardcoded for now because the
* mtd subsystem does not offer finding the partition yet and we do not
* want to reimplement OF partition parser here.
*/

2
board/amlogic/vim3/vim3.c
View file

@ -89,7 +89,7 @@ int meson_ft_board_setup(void *blob, struct bd_info *bd)
/*
* If in PCIe mode, alter DT
* 0：Enable USB3.0，Disable PCIE, 1：Disable USB3.0, Enable PCIE
* 0: Enable USB3.0, Disable PCIE, 1: Disable USB3.0, Enable PCIE
*/
if (ret > 0) {
static char data[32] __aligned(4);

2
board/bosch/acc/acc.c
View file

@ -437,7 +437,7 @@ static const struct mx6_ddr3_cfg acc_mx6d_mem_ddr3_1066 = {
.trcd = 1313, // 13.125ns
.trcmin = 5063, // 50.625ns
.trasmin = 3750, // 37.5ns
.SRT = 0, // Set to 1 for temperatures above 85°C
.SRT = 0, // Set to 1 for temperatures above 85 deg C
};
static const struct mx6_ddr_sysinfo acc_mx6d_ddr_info = {

2
board/bosch/shc/board.c
View file

@ -115,7 +115,7 @@ static void __maybe_unused force_modules_running(void)
gpio_direction_output(WIFI_REGEN_GPIO, 1);
/*
* Wait for Wi-Fi power regulator to reach a stable voltage
* (soft-start time, max. 350 µs)
* (soft-start time, max. 350 us)
*/
__udelay(350);

2
board/bosch/shc/board.h
View file

@ -154,7 +154,7 @@ static inline int board_is_series(void)
#define HDR_FATC_LEN 12
/*
* SHC parameters held in On-Board I²C EEPROM device.
* SHC parameters held in On-Board I2C EEPROM device.
*
* Header Format
*

4
board/congatec/cgtqmx8/cgtqmx8.c
View file

@ -171,7 +171,7 @@ int board_mmc_init(struct bd_info *bis)
* (U-Boot device node) (Physical Port)
* mmc0 (onboard eMMC) USDHC1
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
* mmc2 (onboard uSD) USDHC3
*/
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
@ -196,7 +196,7 @@ int board_mmc_init(struct bd_info *bis)
gpio_direction_input(USDHC1_CD_GPIO);
break;
case 2:
/* onboard µSD */
/* onboard uSD */
if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd))
power_domain_on(&pd);

2
board/freescale/common/i2c_mux.c
View file

@ -12,7 +12,7 @@
/*
* A new Kconfig option for something that used to always be built should be
* “default y”.
* "default y".
*/
#ifdef CONFIG_FSL_USE_PCA9547_MUX

8
board/siemens/capricorn/board.c
View file

@ -156,14 +156,14 @@ int setup_gpr_fec(void)
* 0: internal clock
* 1: external clock ---> your choice for RMII
*
* CLKDIV_SEL: it controls a div by 2 on the internal clock path à
* it should be don’t care when using external clock
* CLKDIV_SEL: it controls a div by 2 on the internal clock path a
* it should be don't care when using external clock
* 0: non-divided clock
* 1: clock divided by 2
* 50_DISABLE or 125_DISABLE:
* it’s used to disable the clock tree going outside the chip
* it's used to disable the clock tree going outside the chip
* when reference clock is generated internally.
* It should be don’t care when reference clock is provided
* It should be don't care when reference clock is provided
* externally.
* 0: clock is enabled
* 1: clock is disabled

2
board/st/common/cmd_stboard.c
View file

@ -9,7 +9,7 @@
* - "Commercial Product Name" (CPN): type of product board (DKX, EVX)
* associated to the board ID "MBxxxx"
* - "Finished Good" or "Finish Good" (FG):
* effective content of the product without chip STM32MP1xx (LCD, Wifi,…)
* effective content of the product without chip STM32MP1xx (LCD, Wifi,...)
* - BOM: cost variant for same FG (for example, several provider of the same
* component)
*

4
board/starfive/visionfive2/visionfive2-i2c-eeprom.c
View file

@ -503,7 +503,7 @@ int mac_read_from_eeprom(void)
* "<product>-<date>-<DDR&eMMC>-<serial_number>"
* <date>: 4Byte, should be the output of `date +%y%W`
* <DDR&eMMC>: 8Byte, "D008" means 8GB, "D01T" means 1TB;
* "E000" means no eMMC，"E032" means 32GB, "E01T" means 1TB.
* "E000" means no eMMC, "E032" means 32GB, "E01T" means 1TB.
* <serial_number>: 8Byte, the Unique Identifier of board in hex.
*/
if (!env_get("serial#"))
@ -533,7 +533,7 @@ u8 get_pcb_revision_from_eeprom(void)
* get_ddr_size_from_eeprom - get the DDR size
* pstr: VF7110A1-2228-D008E000-00000001
* VF7110A1/VF7110B1 : VisionFive JH7110A /VisionFive JH7110B
* D008:　8GB LPDDR4
* D008: 8GB LPDDR4
* E000: No emmc device, ECxx: include emmc device, xx: Capacity size[GB]
* return: the field of 'D008E000'
*/

2
cmd/Kconfig
View file

@ -446,7 +446,7 @@ config CMD_BOOTEFI_HELLO
for testing that EFI is working at a basic level, and for bringing
up EFI support on a new architecture.
source lib/efi_selftest/Kconfig
source "lib/efi_selftest/Kconfig"
endif
config CMD_BOOTMENU

10
drivers/clk/Kconfig
View file

@ -57,27 +57,27 @@ config CLK_BOSTON
Enable this to support the clocks
config SPL_CLK_CCF
bool "SPL Common Clock Framework [CCF] support "
bool "SPL Common Clock Framework [CCF] support"
depends on SPL
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's SPL.
config SPL_CLK_COMPOSITE_CCF
bool "SPL Common Clock Framework [CCF] composite clk support "
bool "SPL Common Clock Framework [CCF] composite clk support"
depends on SPL_CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] composite code in U-Boot's SPL.
config CLK_CCF
bool "Common Clock Framework [CCF] support "
bool "Common Clock Framework [CCF] support"
help
Enable this option if you want to (re-)use the Linux kernel's Common
Clock Framework [CCF] code in U-Boot's clock driver.
config CLK_COMPOSITE_CCF
bool "Common Clock Framework [CCF] composite clk support "
bool "Common Clock Framework [CCF] composite clk support"
depends on CLK_CCF
help
Enable this option if you want to (re-)use the Linux kernel's Common
@ -164,7 +164,7 @@ config CLK_OCTEON
Enable this to support the clocks on Octeon MIPS platforms.
config SANDBOX_CLK_CCF
bool "Sandbox Common Clock Framework [CCF] support "
bool "Sandbox Common Clock Framework [CCF] support"
depends on SANDBOX
select CLK_CCF
help

6
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -313,9 +313,9 @@ static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_
/*
* As per the HW manual, we should not directly switch from 533 MHz to
* 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz)
* to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first,
* and then switch to the target setting (2’b01 (533 MHz) or 2’b10
* 400 MHz and vice versa. To change the setting from 2'b01 (533 MHz)
* to 2'b10 (400 MHz) or vice versa, Switch to 2'b11 (266 MHz) first,
* and then switch to the target setting (2'b01 (533 MHz) or 2'b10
* (400 MHz)).
*/
if (new_sel != SEL_SDHI_266MHz && prev_sel != SEL_SDHI_266MHz) {

22
drivers/clk/stm32/clk-stm32-core.h
View file

@ -178,7 +178,7 @@ int stm32_rcc_init(struct udevice *dev,
* ------------------------------ ----------
* Each peripheral requires a bus interface clock, named ckg_bus_perx
* (for peripheral ‘x’).
* (for peripheral `x').
* Some peripherals (SAI, UART...) need also a dedicated clock for their
* communication interface, this clock is generally asynchronous with respect to
* the bus interface clock, and is named kernel clock (ckg_ker_perx).
@ -188,16 +188,16 @@ int stm32_rcc_init(struct udevice *dev,
* the bus or the Kernel was enable.
*
* Example:
* 1) enable the bus clock
 * --> bus_clk ref_counting = 1, gate_ref_count = 1
 * 2) enable the kernel clock
 * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2
 * 3) disable kernel clock
 *  ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1
 *  ==> then i will not gate because gate_ref_count > 0
 * 4) disable bus clock
 * --> bus_clk ref_counting = 0, gate_ref_count = 0
 * ==> then i can gate (write in the register) because
* 1) enable the bus clock
* --> bus_clk ref_counting = 1, gate_ref_count = 1
* 2) enable the kernel clock
* --> perx_ker_ck ref_counting = 1, gate_ref_count = 2
* 3) disable kernel clock
* ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1
* ==> then i will not gate because gate_ref_count > 0
* 4) disable bus clock
* --> bus_clk ref_counting = 0, gate_ref_count = 0
* ==> then i can gate (write in the register) because
* gate_ref_count = 0
*/

8
drivers/crypto/Kconfig
View file

@ -1,11 +1,11 @@
menu "Hardware crypto devices"
source drivers/crypto/hash/Kconfig
source "drivers/crypto/hash/Kconfig"
source drivers/crypto/fsl/Kconfig
source "drivers/crypto/fsl/Kconfig"
source drivers/crypto/aspeed/Kconfig
source "drivers/crypto/aspeed/Kconfig"
source drivers/crypto/nuvoton/Kconfig
source "drivers/crypto/nuvoton/Kconfig"
endmenu

2
drivers/ddr/imx/imx8ulp/Kconfig
View file

@ -5,7 +5,7 @@ config IMX8ULP_DRAM
bool "imx8m dram"
config IMX8ULP_DRAM_PHY_PLL_BYPASS
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK"
depends on IMX8ULP_DRAM
config SAVED_DRAM_TIMING_BASE

4
drivers/led/led_lp5562.c
View file

@ -125,9 +125,9 @@ static int lp5562_led_reg_update(struct udevice *dev, int regnum,
/*
* Data sheet says "Delay between consecutive I2C writes to
* ENABLE register (00h) need to be longer than 488 μs
* ENABLE register (00h) need to be longer than 488 us
* (typical)." and "Delay between consecutive I2C writes to
* OP_MODE register need to be longer than 153 μs (typ)."
* OP_MODE register need to be longer than 153 us (typ)."
*
* The linux driver does usleep_range(500, 600) and
* usleep_range(200, 300), respectively.

2
drivers/mtd/nand/raw/nand_ids.c
View file

@ -62,7 +62,7 @@ struct nand_flash_dev nand_flash_ids[] = {
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
NAND_ECC_INFO(40, SZ_1K), 4 },
{"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit",
{"H27QCG8T2E5R-BCF 64G 3.3V 8-bit",
{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
NAND_ECC_INFO(56, SZ_1K), 1 },

2
drivers/mtd/spi/Kconfig
View file

@ -246,7 +246,7 @@ config SPI_FLASH_USE_4K_SECTORS
to erasing whole blocks (32/64 KiB).
Changing a small part of the flash's contents is usually faster with
small sectors. On the other hand erasing should be faster when using
64 KiB block instead of 16 × 4 KiB sectors.
64 KiB block instead of 16 x 4 KiB sectors.
Please note that some tools/drivers/filesystems may not work with
4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).

6
drivers/rng/stm32_rng.c
View file

@ -74,7 +74,7 @@ struct stm32_rng_plat {
* Extracts from the STM32 RNG specification when RNG supports CONDRST.
*
* When a noise source (or seed) error occurs, the RNG stops generating
* random numbers and sets to “1” both SEIS and SECS bits to indicate
* random numbers and sets to "1" both SEIS and SECS bits to indicate
* that a seed error occurred. (...)
*
* 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield
@ -127,12 +127,12 @@ static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_plat *pdata)
* Extracts from the STM32 RNG specification, when CONDRST is not supported
*
* When a noise source (or seed) error occurs, the RNG stops generating
* random numbers and sets to “1” both SEIS and SECS bits to indicate
* random numbers and sets to "1" both SEIS and SECS bits to indicate
* that a seed error occurred. (...)
*
* The following sequence shall be used to fully recover from a seed
* error after the RNG initialization:
* 1. Clear the SEIS bit by writing it to “0”.
* 1. Clear the SEIS bit by writing it to "0".
* 2. Read out 12 words from the RNG_DR register, and discard each of
* them in order to clean the pipeline.
* 3. Confirm that SEIS is still cleared. Random number generation is

2
drivers/soc/ti/k3-navss-ringacc.c
View file

@ -418,7 +418,7 @@ void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ)
k3_ringacc_ring_reconfig_qmode_sci(
ring, K3_NAV_RINGACC_RING_MODE_RING);
/*
* 4. Ring the doorbell 2**22 – ringOcc times.
* 4. Ring the doorbell 2**22 - ringOcc times.
* This will wrap the internal UDMAP ring state occupancy
* counter (which is 21-bits wide) to 0.
*/

2
drivers/thermal/thermal_sandbox.c
View file

@ -12,7 +12,7 @@
int sandbox_thermal_get_temp(struct udevice *dev, int *temp)
{
/* Simply return 100°C */
/* Simply return 100 deg C */
*temp = 100;
return 0;

2
drivers/video/renesas-r61307.c
View file

@ -19,7 +19,7 @@
#include <power/regulator.h>
/*
* The datasheet is not publicly available, all values are
* The datasheet is not publicly available, all values are
* taken from the downstream. If you have access to datasheets,
* corrections are welcome.
*/

2
drivers/video/renesas-r69328.c
View file

@ -19,7 +19,7 @@
#include <power/regulator.h>
/*
* The datasheet is not publicly available, all values are
* The datasheet is not publicly available, all values are
* taken from the downstream. If you have access to datasheets,
* corrections are welcome.
*/

2
drivers/xen/pvblock.c
View file

@ -79,7 +79,7 @@ struct blkfront_plat {
};
/**
* struct blkfront_aiocb - AIO сontrol block
* struct blkfront_aiocb - AIO control block
* @aio_dev: Blockfront device
* @aio_buf: Memory buffer, which must be sector-aligned for
* @aio_dev sector

6
include/acpi/acpigen.h
View file

@ -121,7 +121,7 @@ struct acpi_cstate {
*
* @percent: Percent of the core CPU operating frequency that will be
* available when this throttling state is invoked
* @power: Throttling state’s maximum power dissipation (mw)
* @power: Throttling state's maximum power dissipation (mw)
* @latency: Worst-case latency (uS) that the CPU is unavailable during a
* transition from any throttling state to this throttling state
* @control: Value to be written to the Processor Control Register
@ -920,7 +920,7 @@ void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power,
* @ctx: ACPI context pointer
* @domain: Dependency domain number to which this P state entry belongs
* @numprocs: Number of processors belonging to the domain for this logical
* processor’s P-states
* processor's P-states
* @coordtype: Coordination type
*/
void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,
@ -972,7 +972,7 @@ void acpigen_write_tss_package(struct acpi_ctx *ctx,
* @ctx: ACPI context pointer
* @domain: dependency domain number to which this T state entry belongs
* @numprocs: Number of processors belonging to the domain for this logical
* processor’s T-states
* processor's T-states
* @coordtype: Coordination type
*/
void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs,

2
include/linux/mtd/mtd.h
View file

@ -153,7 +153,7 @@ struct mtd_info {
uint32_t flags;
uint64_t size; // Total size of the MTD
/* "Major" erase size for the device. Naïve users may take this
/* "Major" erase size for the device. Naive users may take this
* to be the only erase size available, or may use the more detailed
* information below if they desire
*/

18
lib/Kconfig
View file

@ -416,7 +416,7 @@ config TRACE_EARLY_ADDR
config CIRCBUF
bool "Enable circular buffer support"
source lib/dhry/Kconfig
source "lib/dhry/Kconfig"
menu "Security support"
@ -429,10 +429,10 @@ config AES
supported by the algorithm but only a 128-bit key is supported at
present.
source lib/ecdsa/Kconfig
source lib/rsa/Kconfig
source lib/crypto/Kconfig
source lib/crypt/Kconfig
source "lib/ecdsa/Kconfig"
source "lib/rsa/Kconfig"
source "lib/crypto/Kconfig"
source "lib/crypt/Kconfig"
config TPM
bool "Trusted Platform Module (TPM) Support"
@ -1081,9 +1081,9 @@ config SMBIOS_PARSER
help
A simple parser for SMBIOS data.
source lib/efi/Kconfig
source lib/efi_loader/Kconfig
source lib/optee/Kconfig
source "lib/efi/Kconfig"
source "lib/efi_loader/Kconfig"
source "lib/optee/Kconfig"
config TEST_FDTDEC
bool "enable fdtdec test"
@ -1148,4 +1148,4 @@ config PHANDLE_CHECK_SEQ
endmenu
source lib/fwu_updates/Kconfig
source "lib/fwu_updates/Kconfig"

2
lib/crypto/x509_cert_parser.c
View file

@ -535,7 +535,7 @@ int x509_process_extension(void *context, size_t hdrlen,
* Decode an ASN.1 universal time or generalised time field into a struct the
* kernel can handle and check it for validity. The time is decoded thus:
*
* [RFC5280 §4.1.2.5]
* [RFC5280 paragraph 74.1.2.5]
* CAs conforming to this profile MUST always encode certificate validity
* dates through the year 2049 as UTCTime; certificate validity dates in
* 2050 or later MUST be encoded as GeneralizedTime. Conforming

2
lib/efi_loader/Kconfig
View file

@ -145,7 +145,7 @@ if EFI_VARIABLES_PRESEED
config EFI_VAR_SEED_FILE
string "File with initial values of non-volatile UEFI variables"
default ubootefi.var
default "ubootefi.var"
help
File with initial values of non-volatile UEFI variables. The file must
be in the same format as the storage in the EFI system partition. The