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powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code

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Remove duplicated code in MPC8569MDS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2010-12-17 10:18:07 -06:00
parent 3f6f9d7641
commit 94f2bc4860
3 changed files with 3 additions and 41 deletions
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4
board/freescale/mpc8569mds/law.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright 2009 Freescale Semiconductor, Inc. * Copyright 2009-2010 Freescale Semiconductor, Inc.
* *
* (C) Copyright 2000 * (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -51,8 +51,6 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM #ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
#endif #endif
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
}; };

39
board/freescale/mpc8569mds/mpc8569mds.c
View file

@ -518,51 +518,14 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
clrbits_8(&bcsr[17], BCSR17_nUSBEN); clrbits_8(&bcsr[17], BCSR17_nUSBEN);
} }
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
void pci_init_board(void) void pci_init_board(void)
{ {
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[1];
u32 devdisr, pordevsr, io_sel;
int first_free_busno = 0;
int num = 0;
int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
#if defined(CONFIG_PQ_MDS_PIB) #if defined(CONFIG_PQ_MDS_PIB)
pib_init(); pib_init();
#endif #endif
#ifdef CONFIG_PCIE1 fsl_pcie_init_board(0);
pcie_configured = is_serdes_configured(PCIE1);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf("PCIE1: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
} }
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */

1
include/configs/MPC8569MDS.h
View file

@ -345,6 +345,7 @@ extern unsigned long get_clock_freq(void);
* General PCI * General PCI
* Memory Addresses are mapped 1-1. I/O is mapped from 0 * Memory Addresses are mapped 1-1. I/O is mapped from 0
*/ */
#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000