From d953ef8a2451aa74bc285b201439873735bd5045 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 16 Dec 2023 06:42:28 +0100
Subject: [PATCH 01/40] ARM: imx: Force DRAM regulators into FPWM mode on DH
i.MX8MP DHCOM SoM
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
---
board/dhelectronics/dh_imx8mp/spl.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index 1b05da53c35..21b12a70c8e 100644
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -94,6 +94,11 @@ static int dh_imx8mp_board_power_init(void)
/* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */
pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c);
+ /* DRAM Vdd1 always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d);
+ /* DRAM Vdd2/Vddq always FPWM */
+ pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d);
+
/* Set LDO4 and CONFIG2 to enable the I2C level translator. */
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59);
pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
From 31757f2bea18b7b4dc6eb6dc1838280a587dca79 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Sat, 16 Dec 2023 06:42:29 +0100
Subject: [PATCH 02/40] ARM: imx: Update DRAM timings with inline ECC on DH
i.MX8MP DHCOM SoM
Import DRAM timings generated by the DDR tool 3.31 which introduce assorted
tweaks to the DRAM controller settings. Furthermore, enable DBI to improve
noise resilience of the DRAM bus by reducing the number of bit changes on
the bus.
Reduce the DRAM rate to 3600 MTps to remove all remaining correctable errors
reported by EDAC . It is not entirely clear why the slightly faster setting
does produce sporadic correctable errors, while this one does not, but this
could be related to simpler PLL setting at 3600 MTps.
Enable inline ECC which is necessary to detect ECC errors and collect
statistics by the EDAC driver in Linux. This reduces the DRAM size by
64 MiB for each 512 MiB of DRAM, so for a 4 GiB device the available
DRAM size becomes 3.5 GiB and for 2 GiB device the available DRAM size
becomes 1.8 GiB.
Signed-off-by: Marek Vasut <marex@denx.de>
---
.../dh_imx8mp/imx8mp_dhcom_pdk2.c | 5 +-
board/dhelectronics/dh_imx8mp/lpddr4_timing.h | 6 +
.../dh_imx8mp/lpddr4_timing_2G_32.c | 130 ++++++++-------
.../dh_imx8mp/lpddr4_timing_4G_32.c | 149 +++++++++++-------
board/dhelectronics/dh_imx8mp/spl.c | 28 ++++
configs/imx8mp_dhcom_pdk2_defconfig | 3 +-
configs/imx8mp_dhcom_pdk3_defconfig | 3 +-
7 files changed, 208 insertions(+), 116 deletions(-)
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 5edb85e1de5..5f12d787d38 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <dm.h>
@@ -30,9 +31,11 @@ int mach_cpu_init(void)
int board_phys_sdram_size(phys_size_t *size)
{
const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
+ const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK;
u8 memcfg = dh_get_memcfg();
- *size = (u64)memsz[memcfg] << 20ULL;
+ /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */
+ *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0));
return 0;
}
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
index 7894da3b918..c4d51174a33 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -9,6 +9,12 @@
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
+typedef void (*scrub_func_t)(void);
+extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void);
+extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void);
+
u8 dh_get_memcfg(void);
+#define DDRC_ECCCFG0_ECC_MODE_MASK 0x7
+
#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
index 51b8c4cf7ba..add7a0bf23b 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@@ -14,48 +14,62 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
{ 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
{ 0x3d400134, 0xd100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0x799 },
- { 0x3d400108, 0x810191a },
+ { 0x3d400108, 0x8121b1a },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x13131300 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@@ -74,7 +88,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -99,7 +113,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -269,7 +283,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -315,19 +329,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1057,7 +1067,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1067,25 +1077,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1107,25 +1117,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1147,25 +1157,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1176,7 +1186,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1187,25 +1197,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1695,9 +1705,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1800,8 +1810,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1821,8 +1831,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1841,5 +1851,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_16g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x3ffffff);
+ ddrc_inline_ecc_scrub(0x4000000,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xbffffff);
+ ddrc_inline_ecc_scrub(0xc000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x13ffffff);
+ ddrc_inline_ecc_scrub(0x14000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1bffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x1fffffff);
+}
+#endif
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
index a4c1b121c27..41b078f6e9f 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c
@@ -14,47 +14,66 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
{ 0x3d400020, 0x1323 },
- { 0x3d400024, 0x1c79100 },
- { 0x3d400064, 0x710106 },
+ { 0x3d400024, 0x1b77400 },
+ { 0x3d400064, 0x6d00fc },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400070, 0x7027fd4 },
+#else
{ 0x3d400070, 0x7027f90 },
+#endif
{ 0x3d400074, 0x790 },
- { 0x3d4000d0, 0xc0030720 },
- { 0x3d4000d4, 0xb80000 },
+ { 0x3d4000d0, 0xc00306df },
+ { 0x3d4000d4, 0xb10000 },
{ 0x3d4000dc, 0xe40036 },
- { 0x3d4000e0, 0x330000 },
+ { 0x3d4000e0, 0xf30000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
- { 0x3d400100, 0x1e262028 },
- { 0x3d400104, 0x7073b },
- { 0x3d40010c, 0xe0e000 },
- { 0x3d400110, 0x11040a11 },
+ { 0x3d400100, 0x1d241e26 },
+ { 0x3d400104, 0x70739 },
+ { 0x3d40010c, 0xd0d000 },
+ { 0x3d400110, 0x11040911 },
{ 0x3d400114, 0x2050e0e },
{ 0x3d400118, 0x1010008 },
- { 0x3d40011c, 0x501 },
+ { 0x3d40011c, 0x502 },
{ 0x3d400130, 0x20700 },
- { 0x3d400134, 0xe100002 },
- { 0x3d400138, 0x10d },
- { 0x3d400144, 0xbb005e },
- { 0x3d400180, 0x3a5001c },
- { 0x3d400184, 0x2f071e5 },
+ { 0x3d400134, 0xd100002 },
+ { 0x3d400138, 0x103 },
+ { 0x3d400144, 0xb4005a },
+ { 0x3d400180, 0x384001b },
+ { 0x3d400184, 0x2d06ddd },
{ 0x3d400188, 0x0 },
- { 0x3d400190, 0x49b820c },
+ { 0x3d400190, 0x49f820c },
{ 0x3d400194, 0x80303 },
- { 0x3d4001b4, 0x1b0c },
+ { 0x3d4001b4, 0x1f0c },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
- { 0x3d4001c0, 0x1 },
+ { 0x3d4001c0, 0x7 },
{ 0x3d4001c4, 0x1 },
- { 0x3d4000f4, 0xc99 },
- { 0x3d400108, 0x810191a },
+ { 0x3d4000f4, 0x799 },
+ { 0x3d400108, 0x8121b1a },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400200, 0x14 },
+#else
{ 0x3d400200, 0x17 },
+#endif
+ { 0x3d400208, 0x0 },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d40020c, 0x14141400 },
+#else
{ 0x3d40020c, 0x0 },
+#endif
{ 0x3d400210, 0x1f1f },
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+ { 0x3d400204, 0x50505 },
+ { 0x3d400214, 0x4040404 },
+ { 0x3d400218, 0x4040404 },
+#else
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+#endif
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
@@ -73,7 +92,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc001c },
{ 0x3d4020dc, 0x840000 },
- { 0x3d4020e0, 0x330000 },
+ { 0x3d4020e0, 0xf30000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
@@ -83,7 +102,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
- { 0x3d40211c, 0x301 },
+ { 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x1d },
@@ -92,13 +111,13 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
- { 0x3d4020f4, 0xc99 },
+ { 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30007 },
{ 0x3d4030dc, 0x840000 },
- { 0x3d4030e0, 0x330000 },
+ { 0x3d4030e0, 0xf30000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
@@ -108,7 +127,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
- { 0x3d40311c, 0x301 },
+ { 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x8 },
@@ -117,7 +136,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
- { 0x3d4030f4, 0xc99 },
+ { 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
@@ -268,7 +287,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
- { 0x20008, 0x3a5 },
+ { 0x20008, 0x384 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -314,19 +333,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x12002d, 0x0 },
- { 0x22002d, 0x0 },
+ { 0x2002d, 0x1 },
+ { 0x12002d, 0x1 },
+ { 0x22002d, 0x1 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x1204a, 0x500 },
- { 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
@@ -1056,7 +1071,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1066,25 +1081,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1106,25 +1121,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1146,25 +1161,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{ 0x5400f, 0x100 },
{ 0x54012, 0x310 },
{ 0x54019, 0x84 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0x8400 },
- { 0x54033, 0x3300 },
+ { 0x54033, 0xf300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
- { 0x54039, 0x3300 },
+ { 0x54039, 0xf300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1175,7 +1190,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
- { 0x54003, 0xe94 },
+ { 0x54003, 0xe10 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
@@ -1186,25 +1201,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54010, 0x1f7f },
{ 0x54012, 0x310 },
{ 0x54019, 0x36e4 },
- { 0x5401a, 0x33 },
+ { 0x5401a, 0xf3 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x36e4 },
- { 0x54020, 0x33 },
+ { 0x54020, 0xf3 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x54032, 0xe400 },
- { 0x54033, 0x3336 },
+ { 0x54033, 0xf336 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xe400 },
- { 0x54039, 0x3336 },
+ { 0x54039, 0xf336 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1694,9 +1709,9 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x200be, 0x3 },
- { 0x2000b, 0x419 },
- { 0x2000c, 0xe9 },
- { 0x2000d, 0x91c },
+ { 0x2000b, 0x3f4 },
+ { 0x2000c, 0xe1 },
+ { 0x2000d, 0x8ca },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x70 },
{ 0x12000c, 0x19 },
@@ -1799,8 +1814,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3600mts 1D */
+ .drate = 3600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1820,8 +1835,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3600mts 2D */
+ .drate = 3600,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1840,5 +1855,19 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 400, 100, },
+ .fsp_table = { 3600, 400, 100, },
};
+
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
+{
+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index 21b12a70c8e..7d228da8e5b 100644
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -11,6 +11,7 @@
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
@@ -134,8 +135,35 @@ static void spl_dram_init(void)
}
ddr_init(dram_timing_info[memcfg]);
+
+ printf("DDR: Inline ECC %sabled\n",
+ (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?
+ "en" : "dis");
}
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+static const scrub_func_t dram_scrub_fn[8] = {
+ NULL, /* 512 MiB */
+ NULL, /* 1024 MiB */
+ NULL, /* 1536 MiB */
+ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */
+ NULL, /* 3072 MiB */
+ dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */
+ NULL, /* 6144 MiB */
+ NULL, /* 8192 MiB */
+};
+
+void board_dram_ecc_scrub(void)
+{
+ u8 memcfg = dh_get_memcfg();
+
+ if (!dram_scrub_fn[memcfg])
+ return;
+
+ dram_scrub_fn[memcfg]();
+}
+#endif
+
void spl_board_init(void)
{
/*
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 09481343bc6..e072d7adca0 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -50,7 +50,7 @@ CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -161,6 +161,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 86121c7d9a4..d0ace794bb2 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -51,7 +51,7 @@ CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
+CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
@@ -163,6 +163,7 @@ CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
From 1f25c75619d7fdacbaa8c2c9c152ebc9aec807b3 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Mon, 18 Dec 2023 19:02:14 +0100
Subject: [PATCH 03/40] ARM: dts: imx: Power off display output on Data Modul
i.MX8M Mini/Plus eDM SBC
Turn display connector power off on boot and reboot to prevent any
bogus start up sequence of any panel potentially attached to the
display connector.
Signed-off-by: Marek Vasut <marex@denx.de>
---
.../dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 49 +++++++++++++++++++
.../dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 48 ++++++++++++++++++
2 files changed, 97 insertions(+)
diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
index 144c42b2103..a235e088fa4 100644
--- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
@@ -77,10 +77,59 @@
&gpio2 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
};
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
index eafe9b9308c..a2b5976b6bd 100644
--- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
@@ -67,10 +67,58 @@
&gpio3 {
bootph-pre-ram;
+
+ bl-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ line-name = "BL_ENABLE_1V8";
+ };
+
+ tft-enable-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-low;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ line-name = "TFT_ENABLE_1V8";
+ };
+
+ graphics-gpio0-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ line-name = "GRAPHICS_GPIO0_1V8";
+ };
};
&gpio4 {
bootph-pre-ram;
+
+ dsi-reset-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ output-high;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_RESET_1V8#";
+ };
+
+ graphics-prsnt-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <18 GPIO_ACTIVE_LOW>;
+ line-name = "GRAPHICS_PRSNT_1V8#";
+ };
+
+ dsi-irq-hog {
+ bootph-pre-ram;
+ gpio-hog;
+ input;
+ gpios = <19 GPIO_ACTIVE_LOW>;
+ line-name = "DSI_IRQ_1V8#";
+ };
};
&gpio5 {
From 38003ab25cc5a23335f55977620dc28ac7ca7657 Mon Sep 17 00:00:00 2001
From: Peter Robinson <pbrobinson@gmail.com>
Date: Wed, 22 Nov 2023 22:57:07 +0000
Subject: [PATCH 04/40] doc: Remove README.sha1 file
The contents of README.sha1 only refer to process around verification
of the pcs440ep board firmware in flash. The device was removed in
commit 242836a893ae ("powerpc: ppc4xx: remove pcs440ep support") in
2015 so this readme isn't really relevant anymore so can be removed.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
doc/README.sha1 | 58 -------------------------------------------------
1 file changed, 58 deletions(-)
delete mode 100644 doc/README.sha1
diff --git a/doc/README.sha1 b/doc/README.sha1
deleted file mode 100644
index f178f372643..00000000000
--- a/doc/README.sha1
+++ /dev/null
@@ -1,58 +0,0 @@
-SHA1 usage:
------------
-
-In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated.
-This SHA1 sum is used, to check, if the U-Boot Image in Flash is not
-corrupted.
-
-The following command is available:
-
-=> help sha1
-sha1 address len [addr] calculate the SHA1 sum [save at addr]
- -p calculate the SHA1 sum from the U-Boot image in flash and print
- -c check the U-Boot image in flash
-
-"sha1 -p"
- calculates and prints the SHA1 sum, from the Image stored in Flash
-
-"sha1 -c"
- check, if the SHA1 sum from the Image stored in Flash is correct
-
-
-It is possible to calculate a SHA1 checksum from a memoryrange with:
-
-"sha1 address len"
-
-If you want to store a new Image in Flash for the pcs440ep board,
-which has no SHA1 sum, you can do the following:
-
-a) cp the new Image on a position in RAM (here 0x300000)
- (for this example we use the Image from Flash, stored at 0xfffa0000 and
- 0x60000 Bytes long)
-
-"cp.b fffa0000 300000 60000"
-
-b) Initialize the SHA1 sum in the Image with 0x00
- The SHA1 sum is stored in Flash at:
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS
- for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20
- = 0xffffffe0
- for the example in RAM: 0x300000 + 0x60000 + -0x20
- = 0x35ffe0
-
- note: a SHA1 checksum is 20 bytes long.
-
-"mw.b 35ffe0 0 14"
-
-c) now calculate the SHA1 sum from the memoryrange and write
- the calculated checksum at the right place:
-
-"sha1 300000 60000 35ffe0"
-
-Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum.
-
-If you do a "buildman -k pcs440ep" or a "make all" to get the U-Boot image,
-which will be found in ../current/ipam390/ - the correct SHA1 sum will be
-automagically included in the U-Boot image.
-
-Heiko Schocher, 11 Jul 2007
From fac5308d275720b67b442383572a84edb212d6a1 Mon Sep 17 00:00:00 2001
From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Date: Tue, 19 Dec 2023 09:25:33 +0100
Subject: [PATCH 05/40] arm: dts: k3-am625-verdin: fix DDRSS configuration
The current DDR subsystem configuration occasionally results in write failures,
impacting memory stability, on Verdin AM62 Solo 512MB WB IT 0072 SKU.
This commit addresses the issue by adjusting Drive Pull-Up/Down and
Write Latency to improve the eye diagram and ensure reliable write operations.
This configuration is shared with all Verdin AM62 SoM and
it does not introduce regressions.
Configurations changes from previous / default values:
- Drive Pull-Up/Down from 40 to 34.3 Ohm
- Write Latency from 8 to 10
- ODTLon / ODTLoff latency from 0 / 0 to 4 / 20 nCK
- VREF control range 1 at 27 %
- tFAW from 30 to 40 ns
Configuration is output from SysConfig [1] web tool, currently at version
1.18.1+3343 (DDR SubSystem v9.10).
[1] https://dev.ti.com/sysconfig
Fixes: 7d1a10659f5b ("board: toradex: add verdin am62 support")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
.../dts/k3-am625-verdin-lpddr4-1600MTs.dtsi | 151 +++++++++---------
1 file changed, 76 insertions(+), 75 deletions(-)
diff --git a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
index 9bad4309b49..841541bb243 100644
--- a/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-lpddr4-1600MTs.dtsi
@@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.08
- * Fri Jun 09 2023 08:01:37 GMT+0200 (Central European Summer Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10
+ * Mon Dec 11 2023 17:07:35 GMT+0100 (Central European Standard Time)
* DDR Type: LPDDR4
* F0 = 50MHz F1 = NA F2 = 800MHz
* Density (per channel): 16Gb
* Write DBI: Enable
* Number of Ranks: 1
- */
+*/
#define DDRSS_PLL_FHS_CNT 3
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
+
#define DDRSS_CTL_0_DATA 0x00000B00
#define DDRSS_CTL_1_DATA 0x00000000
#define DDRSS_CTL_2_DATA 0x00000000
@@ -54,20 +55,20 @@
#define DDRSS_CTL_37_DATA 0x00000000
#define DDRSS_CTL_38_DATA 0x0000040C
#define DDRSS_CTL_39_DATA 0x00000000
-#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_40_DATA 0x00000A1C
#define DDRSS_CTL_41_DATA 0x00000000
-#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_42_DATA 0x00000A1C
#define DDRSS_CTL_43_DATA 0x00000000
#define DDRSS_CTL_44_DATA 0x05000804
#define DDRSS_CTL_45_DATA 0x00000B00
#define DDRSS_CTL_46_DATA 0x09090004
-#define DDRSS_CTL_47_DATA 0x00000204
+#define DDRSS_CTL_47_DATA 0x00000304
#define DDRSS_CTL_48_DATA 0x00370008
#define DDRSS_CTL_49_DATA 0x09090024
-#define DDRSS_CTL_50_DATA 0x00001910
+#define DDRSS_CTL_50_DATA 0x00002110
#define DDRSS_CTL_51_DATA 0x00370008
#define DDRSS_CTL_52_DATA 0x09090024
-#define DDRSS_CTL_53_DATA 0x09001910
+#define DDRSS_CTL_53_DATA 0x09002110
#define DDRSS_CTL_54_DATA 0x000A0A09
#define DDRSS_CTL_55_DATA 0x0400036D
#define DDRSS_CTL_56_DATA 0x09092004
@@ -223,19 +224,19 @@
#define DDRSS_CTL_206_DATA 0x00000000
#define DDRSS_CTL_207_DATA 0x00000000
#define DDRSS_CTL_208_DATA 0x00000024
-#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_209_DATA 0x0000001A
#define DDRSS_CTL_210_DATA 0x00000000
#define DDRSS_CTL_211_DATA 0x00000024
-#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_212_DATA 0x0000001A
#define DDRSS_CTL_213_DATA 0x00000000
#define DDRSS_CTL_214_DATA 0x00000004
#define DDRSS_CTL_215_DATA 0x00000000
#define DDRSS_CTL_216_DATA 0x00000000
#define DDRSS_CTL_217_DATA 0x00000024
-#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_218_DATA 0x0000001A
#define DDRSS_CTL_219_DATA 0x00000000
#define DDRSS_CTL_220_DATA 0x00000024
-#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_221_DATA 0x0000001A
#define DDRSS_CTL_222_DATA 0x00000000
#define DDRSS_CTL_223_DATA 0x00000000
#define DDRSS_CTL_224_DATA 0x00000031
@@ -268,21 +269,21 @@
#define DDRSS_CTL_251_DATA 0x00000000
#define DDRSS_CTL_252_DATA 0x00000000
#define DDRSS_CTL_253_DATA 0x00000000
-#define DDRSS_CTL_254_DATA 0x46004646
-#define DDRSS_CTL_255_DATA 0x00002746
-#define DDRSS_CTL_256_DATA 0x00000027
-#define DDRSS_CTL_257_DATA 0x00000027
-#define DDRSS_CTL_258_DATA 0x00000027
-#define DDRSS_CTL_259_DATA 0x00000027
-#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_254_DATA 0x44004444
+#define DDRSS_CTL_255_DATA 0x00004D44
+#define DDRSS_CTL_256_DATA 0x0000004D
+#define DDRSS_CTL_257_DATA 0x0000004D
+#define DDRSS_CTL_258_DATA 0x0000004D
+#define DDRSS_CTL_259_DATA 0x0000004D
+#define DDRSS_CTL_260_DATA 0x0000004D
#define DDRSS_CTL_261_DATA 0x00000000
#define DDRSS_CTL_262_DATA 0x00000000
-#define DDRSS_CTL_263_DATA 0x0000000F
-#define DDRSS_CTL_264_DATA 0x0000000F
-#define DDRSS_CTL_265_DATA 0x0000000F
-#define DDRSS_CTL_266_DATA 0x0000000F
-#define DDRSS_CTL_267_DATA 0x0000000F
-#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_263_DATA 0x0000004D
+#define DDRSS_CTL_264_DATA 0x0000004D
+#define DDRSS_CTL_265_DATA 0x0000004D
+#define DDRSS_CTL_266_DATA 0x0000004D
+#define DDRSS_CTL_267_DATA 0x0000004D
+#define DDRSS_CTL_268_DATA 0x0000004D
#define DDRSS_CTL_269_DATA 0x00000000
#define DDRSS_CTL_270_DATA 0x00001000
#define DDRSS_CTL_271_DATA 0x00000015
@@ -388,13 +389,13 @@
#define DDRSS_CTL_371_DATA 0x01000101
#define DDRSS_CTL_372_DATA 0x01010001
#define DDRSS_CTL_373_DATA 0x00010101
-#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_374_DATA 0x01070703
#define DDRSS_CTL_375_DATA 0x05020201
#define DDRSS_CTL_376_DATA 0x08080C0C
#define DDRSS_CTL_377_DATA 0x00080308
-#define DDRSS_CTL_378_DATA 0x000B030E
-#define DDRSS_CTL_379_DATA 0x000B0310
-#define DDRSS_CTL_380_DATA 0x0B0B0810
+#define DDRSS_CTL_378_DATA 0x0009030E
+#define DDRSS_CTL_379_DATA 0x00090312
+#define DDRSS_CTL_380_DATA 0x09090806
#define DDRSS_CTL_381_DATA 0x01000000
#define DDRSS_CTL_382_DATA 0x03020301
#define DDRSS_CTL_383_DATA 0x04000102
@@ -416,7 +417,7 @@
#define DDRSS_CTL_399_DATA 0x00003690
#define DDRSS_CTL_400_DATA 0x00007940
#define DDRSS_CTL_401_DATA 0x070D0402
-#define DDRSS_CTL_402_DATA 0x00260405
+#define DDRSS_CTL_402_DATA 0x00260607
#define DDRSS_CTL_403_DATA 0x00000C20
#define DDRSS_CTL_404_DATA 0x00000200
#define DDRSS_CTL_405_DATA 0x00000200
@@ -425,7 +426,7 @@
#define DDRSS_CTL_408_DATA 0x00003690
#define DDRSS_CTL_409_DATA 0x00007940
#define DDRSS_CTL_410_DATA 0x070D0402
-#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_411_DATA 0x00000607
#define DDRSS_CTL_412_DATA 0x00000000
#define DDRSS_CTL_413_DATA 0x0302000A
#define DDRSS_CTL_414_DATA 0x01000500
@@ -609,8 +610,8 @@
#define DDRSS_PI_169_DATA 0x00020043
#define DDRSS_PI_170_DATA 0x02000200
#define DDRSS_PI_171_DATA 0x00000004
-#define DDRSS_PI_172_DATA 0x0000080C
-#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_172_DATA 0x00000A0C
+#define DDRSS_PI_173_DATA 0x000A1C00
#define DDRSS_PI_174_DATA 0x001C0000
#define DDRSS_PI_175_DATA 0x00000013
#define DDRSS_PI_176_DATA 0x00000059
@@ -624,15 +625,15 @@
#define DDRSS_PI_184_DATA 0x01000100
#define DDRSS_PI_185_DATA 0x00000100
#define DDRSS_PI_186_DATA 0x00000000
-#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_187_DATA 0x05070703
#define DDRSS_PI_188_DATA 0x01010C0C
#define DDRSS_PI_189_DATA 0x01010101
#define DDRSS_PI_190_DATA 0x000C0C0A
#define DDRSS_PI_191_DATA 0x00000000
#define DDRSS_PI_192_DATA 0x00000000
#define DDRSS_PI_193_DATA 0x04000000
-#define DDRSS_PI_194_DATA 0x04020808
-#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_194_DATA 0x06020808
+#define DDRSS_PI_195_DATA 0x04040206
#define DDRSS_PI_196_DATA 0x00090031
#define DDRSS_PI_197_DATA 0x00110039
#define DDRSS_PI_198_DATA 0x00110039
@@ -661,13 +662,13 @@
#define DDRSS_PI_221_DATA 0x00001900
#define DDRSS_PI_222_DATA 0x32000056
#define DDRSS_PI_223_DATA 0x06000101
-#define DDRSS_PI_224_DATA 0x001D0204
-#define DDRSS_PI_225_DATA 0x32120058
+#define DDRSS_PI_224_DATA 0x001F0204
+#define DDRSS_PI_225_DATA 0x72400056
#define DDRSS_PI_226_DATA 0x05000101
-#define DDRSS_PI_227_DATA 0x001D0408
-#define DDRSS_PI_228_DATA 0x32120058
+#define DDRSS_PI_227_DATA 0x001F0608
+#define DDRSS_PI_228_DATA 0x72400056
#define DDRSS_PI_229_DATA 0x05000101
-#define DDRSS_PI_230_DATA 0x00000408
+#define DDRSS_PI_230_DATA 0x00000608
#define DDRSS_PI_231_DATA 0x05040900
#define DDRSS_PI_232_DATA 0x00060900
#define DDRSS_PI_233_DATA 0x00000315
@@ -741,23 +742,23 @@
#define DDRSS_PI_301_DATA 0x00000000
#define DDRSS_PI_302_DATA 0x00000000
#define DDRSS_PI_303_DATA 0x00000000
-#define DDRSS_PI_304_DATA 0x00100F27
+#define DDRSS_PI_304_DATA 0x00104D4D
#define DDRSS_PI_305_DATA 0x00000000
#define DDRSS_PI_306_DATA 0x00000024
-#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_307_DATA 0x0000001A
#define DDRSS_PI_308_DATA 0x000000B1
#define DDRSS_PI_309_DATA 0x00000000
#define DDRSS_PI_310_DATA 0x00000000
-#define DDRSS_PI_311_DATA 0x46000000
-#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_311_DATA 0x44000000
+#define DDRSS_PI_312_DATA 0x00154D4D
#define DDRSS_PI_313_DATA 0x00000000
#define DDRSS_PI_314_DATA 0x00000024
-#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_315_DATA 0x0000001A
#define DDRSS_PI_316_DATA 0x000000B1
#define DDRSS_PI_317_DATA 0x00000000
#define DDRSS_PI_318_DATA 0x00000000
-#define DDRSS_PI_319_DATA 0x46000000
-#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_319_DATA 0x44000000
+#define DDRSS_PI_320_DATA 0x00154D4D
#define DDRSS_PI_321_DATA 0x00000000
#define DDRSS_PI_322_DATA 0x00000004
#define DDRSS_PI_323_DATA 0x00000000
@@ -765,23 +766,23 @@
#define DDRSS_PI_325_DATA 0x00000000
#define DDRSS_PI_326_DATA 0x00000000
#define DDRSS_PI_327_DATA 0x00000000
-#define DDRSS_PI_328_DATA 0x00100F27
+#define DDRSS_PI_328_DATA 0x00104D4D
#define DDRSS_PI_329_DATA 0x00000000
#define DDRSS_PI_330_DATA 0x00000024
-#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_331_DATA 0x0000001A
#define DDRSS_PI_332_DATA 0x000000B1
#define DDRSS_PI_333_DATA 0x00000000
#define DDRSS_PI_334_DATA 0x00000000
-#define DDRSS_PI_335_DATA 0x46000000
-#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_335_DATA 0x44000000
+#define DDRSS_PI_336_DATA 0x00154D4D
#define DDRSS_PI_337_DATA 0x00000000
#define DDRSS_PI_338_DATA 0x00000024
-#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_339_DATA 0x0000001A
#define DDRSS_PI_340_DATA 0x000000B1
#define DDRSS_PI_341_DATA 0x00000000
#define DDRSS_PI_342_DATA 0x00000000
-#define DDRSS_PI_343_DATA 0x46000000
-#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PI_343_DATA 0x44000000
+#define DDRSS_PI_344_DATA 0x00154D4D
#define DDRSS_PHY_0_DATA 0x04F00000
#define DDRSS_PHY_1_DATA 0x00000000
#define DDRSS_PHY_2_DATA 0x00030200
@@ -856,8 +857,8 @@
#define DDRSS_PHY_71_DATA 0x00000000
#define DDRSS_PHY_72_DATA 0x041F07FF
#define DDRSS_PHY_73_DATA 0x00000000
-#define DDRSS_PHY_74_DATA 0x01CC0B01
-#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_74_DATA 0x01FF0B01
+#define DDRSS_PHY_75_DATA 0x1003FF0B
#define DDRSS_PHY_76_DATA 0x20000140
#define DDRSS_PHY_77_DATA 0x07FF0200
#define DDRSS_PHY_78_DATA 0x0000DD01
@@ -872,7 +873,7 @@
#define DDRSS_PHY_87_DATA 0x02020010
#define DDRSS_PHY_88_DATA 0x51516041
#define DDRSS_PHY_89_DATA 0x31C06000
-#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_90_DATA 0x06B60340
#define DDRSS_PHY_91_DATA 0x0000C0C0
#define DDRSS_PHY_92_DATA 0x04050000
#define DDRSS_PHY_93_DATA 0x00000504
@@ -1112,8 +1113,8 @@
#define DDRSS_PHY_327_DATA 0x00000000
#define DDRSS_PHY_328_DATA 0x041F07FF
#define DDRSS_PHY_329_DATA 0x00000000
-#define DDRSS_PHY_330_DATA 0x01CC0B01
-#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_330_DATA 0x01FF0B01
+#define DDRSS_PHY_331_DATA 0x1003FF0B
#define DDRSS_PHY_332_DATA 0x20000140
#define DDRSS_PHY_333_DATA 0x07FF0200
#define DDRSS_PHY_334_DATA 0x0000DD01
@@ -1128,7 +1129,7 @@
#define DDRSS_PHY_343_DATA 0x02020010
#define DDRSS_PHY_344_DATA 0x51516041
#define DDRSS_PHY_345_DATA 0x31C06000
-#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_346_DATA 0x06B60340
#define DDRSS_PHY_347_DATA 0x0000C0C0
#define DDRSS_PHY_348_DATA 0x04050000
#define DDRSS_PHY_349_DATA 0x00000504
@@ -1326,7 +1327,7 @@
#define DDRSS_PHY_541_DATA 0x003F0000
#define DDRSS_PHY_542_DATA 0x000F013F
#define DDRSS_PHY_543_DATA 0x0000000F
-#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_544_DATA 0x020002FF
#define DDRSS_PHY_545_DATA 0x00030000
#define DDRSS_PHY_546_DATA 0x00000300
#define DDRSS_PHY_547_DATA 0x00000300
@@ -1582,7 +1583,7 @@
#define DDRSS_PHY_797_DATA 0x00000000
#define DDRSS_PHY_798_DATA 0x000F0000
#define DDRSS_PHY_799_DATA 0x0000000F
-#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_800_DATA 0x020002FF
#define DDRSS_PHY_801_DATA 0x00030000
#define DDRSS_PHY_802_DATA 0x00000300
#define DDRSS_PHY_803_DATA 0x00000300
@@ -1838,7 +1839,7 @@
#define DDRSS_PHY_1053_DATA 0x10000000
#define DDRSS_PHY_1054_DATA 0x000F0000
#define DDRSS_PHY_1055_DATA 0x0000000F
-#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1056_DATA 0x020002FF
#define DDRSS_PHY_1057_DATA 0x00030000
#define DDRSS_PHY_1058_DATA 0x00000300
#define DDRSS_PHY_1059_DATA 0x00000300
@@ -2169,22 +2170,22 @@
#define DDRSS_PHY_1384_DATA 0x00000300
#define DDRSS_PHY_1385_DATA 0x00000300
#define DDRSS_PHY_1386_DATA 0x00000300
-#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1387_DATA 0x31833F77
#define DDRSS_PHY_1388_DATA 0x00000000
-#define DDRSS_PHY_1389_DATA 0x0C000DFF
-#define DDRSS_PHY_1390_DATA 0x30000DFF
-#define DDRSS_PHY_1391_DATA 0x3F0DFF11
-#define DDRSS_PHY_1392_DATA 0x01990000
-#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1389_DATA 0x0C000DBF
+#define DDRSS_PHY_1390_DATA 0x30000DBF
+#define DDRSS_PHY_1391_DATA 0x3F0DBF11
+#define DDRSS_PHY_1392_DATA 0x01FF0000
+#define DDRSS_PHY_1393_DATA 0x780DBFFF
#define DDRSS_PHY_1394_DATA 0x00000C11
#define DDRSS_PHY_1395_DATA 0x00018011
#define DDRSS_PHY_1396_DATA 0x0089FF00
#define DDRSS_PHY_1397_DATA 0x000C3F11
-#define DDRSS_PHY_1398_DATA 0x01990000
-#define DDRSS_PHY_1399_DATA 0x000C3F11
-#define DDRSS_PHY_1400_DATA 0x01990000
-#define DDRSS_PHY_1401_DATA 0x3F0DFF11
-#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1398_DATA 0x01FF0000
+#define DDRSS_PHY_1399_DATA 0x000C3F91
+#define DDRSS_PHY_1400_DATA 0x01FF0000
+#define DDRSS_PHY_1401_DATA 0x3F0DBF11
+#define DDRSS_PHY_1402_DATA 0x01FF0000
#define DDRSS_PHY_1403_DATA 0x00018011
#define DDRSS_PHY_1404_DATA 0x0089FF00
#define DDRSS_PHY_1405_DATA 0x20040004
From 4caacb2f29f03e7ad724233282384be10c68e926 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 13 Dec 2023 22:11:13 +0100
Subject: [PATCH 06/40] net: wget: Support non-default HTTP port
Currently the wget command is hard wired to HTTP port 80. This is
inconvenient, as it is extremely easy to start trivial HTTP server
as an unprivileged user using e.g. python http module to serve the
files, but such a server has to run on one of the higher ports:
"
$ python3 -m http.server -d $(pwd) 8080
"
Make it possible to configure HTTP server port the same way it is
possible to configure TFTP server port, using environment variable
'httpdstp' (similar to 'tftpdstp'). Retain port 80 as the default
fallback port. This way, users can start their own trivial server
and conveniently download whatever files they need into U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
---
doc/usage/cmd/wget.rst | 3 ++-
doc/usage/environment.rst | 4 ++++
include/net/wget.h | 1 -
net/wget.c | 14 ++++++++++----
4 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst
index e1e7f8d8145..8e7383b6c60 100644
--- a/doc/usage/cmd/wget.rst
+++ b/doc/usage/cmd/wget.rst
@@ -16,7 +16,8 @@ Description
The wget command is used to download a file from an HTTP server.
wget command will use HTTP over TCP to download files from an HTTP server.
-Currently it can only download image from an HTTP server hosted on port 80.
+By default the destination port is 80 and the source port is pseudo-random.
+The environment variable *httpdstp* can be used to set the destination port.
address
memory address for the data downloaded
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index c57b717caaf..82b6ea7b6e7 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -306,6 +306,10 @@ ethrotate
anything other than "no", U-Boot does go through all
available network interfaces.
+httpdstp
+ If this is set, the value is used for HTTP's TCP
+ destination port instead of the default port 80.
+
netretry
When set to "no" each network operation will
either succeed or fail without retrying.
diff --git a/include/net/wget.h b/include/net/wget.h
index da0920de118..6714f7ea573 100644
--- a/include/net/wget.h
+++ b/include/net/wget.h
@@ -17,6 +17,5 @@ enum wget_state {
};
#define DEBUG_WGET 0 /* Set to 1 for debug messages */
-#define SERVER_PORT 80
#define WGET_RETRY_COUNT 30
#define WGET_TIMEOUT 2000UL
diff --git a/net/wget.c b/net/wget.c
index 8bb4d72db1a..e1e580c8351 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -14,6 +14,9 @@
#include <net/tcp.h>
#include <net/wget.h>
+/* The default, change with environment variable 'httpdstp' */
+#define SERVER_PORT 80
+
static const char bootfile1[] = "GET ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
static const char http_eom[] = "\r\n\r\n";
@@ -91,19 +94,22 @@ static void wget_send_stored(void)
int len = retry_len;
unsigned int tcp_ack_num = retry_tcp_seq_num + (len == 0 ? 1 : len);
unsigned int tcp_seq_num = retry_tcp_ack_num;
+ unsigned int server_port;
uchar *ptr, *offset;
+ server_port = env_get_ulong("httpdstp", 10, SERVER_PORT) & 0xffff;
+
switch (current_wget_state) {
case WGET_CLOSED:
debug_cond(DEBUG_WGET, "wget: send SYN\n");
current_wget_state = WGET_CONNECTING;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
packets = 0;
break;
case WGET_CONNECTING:
pkt_q_idx = 0;
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
ptr = net_tx_packet + net_eth_hdr_size() +
@@ -118,14 +124,14 @@ static void wget_send_stored(void)
memcpy(offset, &bootfile3, strlen(bootfile3));
offset += strlen(bootfile3);
- net_send_tcp_packet((offset - ptr), SERVER_PORT, our_port,
+ net_send_tcp_packet((offset - ptr), server_port, our_port,
TCP_PUSH, tcp_seq_num, tcp_ack_num);
current_wget_state = WGET_CONNECTED;
break;
case WGET_CONNECTED:
case WGET_TRANSFERRING:
case WGET_TRANSFERRED:
- net_send_tcp_packet(0, SERVER_PORT, our_port, action,
+ net_send_tcp_packet(0, server_port, our_port, action,
tcp_seq_num, tcp_ack_num);
break;
}
From b5712acb972918a4402971c3cc5a5732d37c3e89 Mon Sep 17 00:00:00 2001
From: Baruch Siach <baruch@tkos.co.il>
Date: Mon, 18 Dec 2023 09:37:53 +0200
Subject: [PATCH 07/40] net: fix NetConsole documentation reference
Fixes: d0253f7e5ca1 ("doc: move README.NetConsole to HTML documentation")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
---
net/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/Kconfig b/net/Kconfig
index 4215889127c..92a22ac1ea5 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -57,7 +57,7 @@ config NETCONSOLE
bool "NetConsole support"
help
Support the 'nc' input/output device for networked console.
- See README.NetConsole for details.
+ See doc/usage/netconsole.rst for details.
config IP_DEFRAG
bool "Support IP datagram reassembly"
From 8f5043ee6d378d7c10d947cf48b047a5954ef5b3 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sat, 16 Dec 2023 19:07:52 +0100
Subject: [PATCH 08/40] get_maintainer.pl: Add --git to look up CCed in git
history
Add the --git parameter, else recent contributors are left out of the CC list.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
.get_maintainer.conf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.get_maintainer.conf b/.get_maintainer.conf
index df595f5420d..f916cfbe480 100644
--- a/.get_maintainer.conf
+++ b/.get_maintainer.conf
@@ -1 +1 @@
---find-maintainer-files --maintainer-path=.
+--find-maintainer-files --git --maintainer-path=.
From f03e3f0b8b2275733d5e299efedaecce42b3db31 Mon Sep 17 00:00:00 2001
From: Jim Liu <jim.t90615@gmail.com>
Date: Tue, 26 Dec 2023 10:00:06 +0800
Subject: [PATCH 09/40] spi: npcm_pspi: Fix the wrong clock divider calculation
Fix the wrong clock divider calculation.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
---
drivers/spi/npcm_pspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c
index 37bab709672..eb14185273e 100644
--- a/drivers/spi/npcm_pspi.c
+++ b/drivers/spi/npcm_pspi.c
@@ -144,7 +144,7 @@ static int npcm_pspi_set_speed(struct udevice *bus, uint speed)
if (speed > priv->max_hz)
speed = priv->max_hz;
- divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1);
+ divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed)) - 1;
if (divisor > MAX_DIV)
divisor = MAX_DIV;
From 0a0ceea2269b983e736b80104f03cc800d1a5e2a Mon Sep 17 00:00:00 2001
From: Mark Kettenis <kettenis@openbsd.org>
Date: Sun, 24 Dec 2023 19:12:55 +0100
Subject: [PATCH 10/40] arm: apple: Disable SMBIOS again
Apple machines do not have memory below 4G. Since U-Boot does
not support the SMBIOS 3 header structures this means we can't
support SMBIOS on these machines. Unfortunately the refactoring
of the SMBIOS code this cycle accidentally enabled it again.
Fixes: 53fab13a7b1 ("efi: Use the installed SMBIOS tables")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
configs/apple_m1_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig
index d58a9030dbd..b868d0e3194 100644
--- a/configs/apple_m1_defconfig
+++ b/configs/apple_m1_defconfig
@@ -21,5 +21,5 @@ CONFIG_USB_KEYBOARD=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
-# CONFIG_GENERATE_SMBIOS_TABLE is not set
+# CONFIG_SMBIOS is not set
CONFIG_LMB_MAX_REGIONS=64
From 88af4d46c601fb1cbb4cac3f8e1cd366711fcb3a Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:46:58 -0600
Subject: [PATCH 11/40] configs: am65x_evm_r5: enable driver for fixed
regulators
Some of the regulators we need to successfully boot are fixed
regulators. Enable the driver to properly probe them.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
configs/am65x_evm_r5_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index b2f1e721b36..b892f2eb8c5 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -118,6 +118,8 @@ CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_TPS62360=y
From 60f04320c0a5a5e3317a83f14b27060a3e044efa Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:46:59 -0600
Subject: [PATCH 12/40] configs: am65x_evm_a53: disable CONSOLE_MUX
We do not have a need to share a single console with the evaluation
board and disabling this option reduces the complexity of configuring
the consoles. Disable CONSOLE_MUX
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
configs/am65x_evm_a53_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index f4369865bf6..4d95e3bd296 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -36,7 +36,6 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run boot_rprocs; if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_overlaystring; run run_fit; else; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; fi;"
CONFIG_LOGLEVEL=7
-CONFIG_CONSOLE_MUX=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
From b53f19061fc4d0a18e58fff84d68f465b1d387ee Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:00 -0600
Subject: [PATCH 13/40] arm: dts: k3-am654-r5: Merge board file and U-Boot
overlay
The R5 board file for U-Boot should be the same as the board file copied
from Linux with a few alterations to work with the R5's view of the SoC.
First we need to unify the R5 board file and it's U-Boot overlay before
we can unify the Linux board file with this one.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 1 -
.../dts/k3-am654-r5-base-board-u-boot.dtsi | 208 ------------------
arch/arm/dts/k3-am654-r5-base-board.dts | 124 ++++++++++-
3 files changed, 119 insertions(+), 214 deletions(-)
delete mode 100644 arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 11d83927ac5..f29cecf870b 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -3,7 +3,6 @@
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include "k3-am654-r5-base-board-u-boot.dtsi"
#include "k3-am65x-binman.dtsi"
&pru0_0 {
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
deleted file mode 100644
index 286604576e0..00000000000
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/pinctrl/k3.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am65x-binman.dtsi"
-
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- };
-
- aliases {
- serial2 = &main_uart0;
- ethernet0 = &cpsw_port1;
- usb0 = &usb0;
- usb1 = &usb1;
- spi0 = &ospi0;
- spi1 = &ospi1;
- };
-};
-
-&cbass_main{
- bootph-pre-ram;
- main_navss: bus@30800000 {
- bootph-pre-ram;
- };
-};
-
-&cbass_mcu {
- bootph-pre-ram;
-
- mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
- ti,dma-ring-reset-quirk;
- };
-
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- bootph-pre-ram;
- };
- };
-};
-
-&cbass_wakeup {
- bootph-pre-ram;
-
- chipid@43000014 {
- bootph-pre-ram;
- };
-};
-
-&secure_proxy_main {
- bootph-pre-ram;
-};
-
-&dmsc {
- bootph-pre-ram;
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
-};
-
-&k3_pds {
- bootph-pre-ram;
-};
-
-&k3_clks {
- bootph-pre-ram;
-};
-
-&k3_reset {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- bootph-pre-ram;
-
- wkup_i2c0_pins_default {
- bootph-pre-ram;
- };
-};
-
-&main_pmx0 {
- bootph-pre-ram;
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- bootph-pre-ram;
- };
-};
-
-&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_pmx1 {
- bootph-pre-ram;
-};
-
-&wkup_pmx0 {
- mcu-fss0-ospi0-pins-default {
- bootph-pre-ram;
- };
-};
-
-&main_uart0 {
- bootph-pre-ram;
-};
-
-&main_mmc0_pins_default {
- bootph-pre-ram;
-};
-
-&main_mmc1_pins_default {
- bootph-pre-ram;
-};
-
-&sdhci0 {
- bootph-pre-ram;
-};
-
-&sdhci1 {
- bootph-pre-ram;
-};
-
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&mcu_cpsw {
- reg = <0x0 0x46000000 0x0 0x200000>,
- <0x0 0x40f00200 0x0 0x2>;
- reg-names = "cpsw_nuss", "mac_efuse";
- /delete-property/ ranges;
-
- cpsw-phy-sel@40f04040 {
- compatible = "ti,am654-cpsw-phy-sel";
- reg= <0x0 0x40f04040 0x0 0x4>;
- reg-names = "gmii-sel";
- };
-};
-
-&wkup_i2c0 {
- bootph-pre-ram;
-};
-
-&usb1 {
- dr_mode = "peripheral";
-};
-
-&fss {
- bootph-pre-ram;
-};
-
-&ospi0 {
- bootph-pre-ram;
-
- flash@0{
- bootph-pre-ram;
- };
-};
-
-&dwc3_0 {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0_phy {
- status = "okay";
- bootph-pre-ram;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&scm_conf {
- bootph-pre-ram;
-};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 637a5cc85e0..d75c7bf3fe6 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -14,9 +14,16 @@
model = "Texas Instruments AM654 R5 Base Board";
aliases {
+ ethernet0 = &cpsw_port1;
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
+ spi0 = &ospi0;
+ spi1 = &ospi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
};
chosen {
@@ -24,11 +31,6 @@
tick-timer = &timer1;
};
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a53_0;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -56,6 +58,8 @@
};
&cbass_main {
+ bootph-pre-ram;
+
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
@@ -63,9 +67,15 @@
clock-frequency = <25000000>;
bootph-all;
};
+
+ main_navss: bus@30800000 {
+ bootph-pre-ram;
+ };
};
&cbass_mcu {
+ bootph-pre-ram;
+
mcu_secproxy: secproxy@28380000 {
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
@@ -75,13 +85,58 @@
#mbox-cells = <1>;
bootph-pre-ram;
};
+
+ mcu_navss: bus@28380000 {
+ bootph-pre-ram;
+
+ ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ bootph-pre-ram;
+ ti,dma-ring-reset-quirk;
+ };
+
+ dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-pre-ram;
+ };
+ };
+};
+
+&k3_pds {
+ bootph-pre-ram;
+};
+
+&k3_clks {
+ bootph-pre-ram;
+};
+
+&k3_reset {
+ bootph-pre-ram;
};
&wkup_gpio0 {
bootph-pre-ram;
};
+&secure_proxy_main {
+ bootph-pre-ram;
+};
+
&cbass_wakeup {
+ bootph-pre-ram;
+
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
@@ -95,13 +150,24 @@
clock-frequency = <200000000>;
bootph-pre-ram;
};
+
+ chipid@43000014 {
+ bootph-pre-ram;
+ };
};
&dmsc {
+ bootph-pre-ram;
+
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
+
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-pre-ram;
+ };
};
&wkup_uart0 {
@@ -125,6 +191,7 @@
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
status = "okay";
+ bootph-pre-ram;
};
&wkup_vtm0 {
@@ -168,6 +235,7 @@
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
+ bootph-pre-ram;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
@@ -184,6 +252,7 @@
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
>;
+ bootph-pre-ram;
};
};
@@ -229,6 +298,17 @@
>;
bootph-pre-ram;
};
+
+ usb0_pins_default: usb0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+ >;
+ bootph-pre-ram;
+ };
+};
+
+&main_pmx1 {
+ bootph-pre-ram;
};
&memorycontroller {
@@ -243,6 +323,7 @@
pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
+ bootph-pre-ram;
};
&sdhci1 {
@@ -251,6 +332,7 @@
pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
+ bootph-pre-ram;
};
&wkup_i2c0 {
@@ -276,6 +358,7 @@
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+ bootph-pre-ram;
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
@@ -293,6 +376,7 @@
cdns,read-delay = <0>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-pre-ram;
};
};
@@ -331,3 +415,33 @@
&scm_conf {
bootph-pre-ram;
};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&mcu_cpsw {
+ reg = <0x0 0x46000000 0x0 0x200000>,
+ <0x0 0x40f00200 0x0 0x2>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@40f04040 {
+ compatible = "ti,am654-cpsw-phy-sel";
+ reg= <0x0 0x40f04040 0x0 0x4>;
+ reg-names = "gmii-sel";
+ };
+};
+
+&usb1 {
+ dr_mode = "peripheral";
+};
+
+&fss {
+ bootph-pre-ram;
+};
From 4dbdc84754ea2ad392ef7328da6d429cd8fd3c0a Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:01 -0600
Subject: [PATCH 14/40] arm: dts: k3-am654: pull in dtb update from Linux
Pull in dtb updates for the am654 base board from v6.7-rc1 of Linux
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am65-main.dtsi | 342 ++++++++++++++++++++++-----
arch/arm/dts/k3-am65-mcu.dtsi | 156 ++++++++++--
arch/arm/dts/k3-am65-wakeup.dtsi | 10 +-
arch/arm/dts/k3-am65.dtsi | 19 +-
arch/arm/dts/k3-am654-base-board.dts | 301 ++++++++++++++---------
arch/arm/dts/k3-am654.dtsi | 7 +
6 files changed, 626 insertions(+), 209 deletions(-)
diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index ba4e5d3e1ed..5ebb87f467d 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -35,7 +35,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01880000 0x00 0x90000>; /* GICR */
+ <0x00 0x01880000 0x00 0x90000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
@@ -88,6 +91,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -96,6 +100,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -104,29 +109,47 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
crypto: crypto@4e00000 {
compatible = "ti,am654-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
- <&main_udmap 0x4001>;
+ dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
+ <&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
- dma-coherent;
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x0 0x4e10000 0x0 0x7d>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 136 1>;
+ status = "disabled"; /* Used by OP-TEE */
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x30>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
@@ -152,6 +175,7 @@
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -163,6 +187,7 @@
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -174,6 +199,7 @@
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -185,6 +211,7 @@
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ecap0: pwm@3100000 {
@@ -194,6 +221,7 @@
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@2100000 {
@@ -206,6 +234,7 @@
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@2110000 {
@@ -218,6 +247,7 @@
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
+ status = "disabled";
};
main_spi2: spi@2120000 {
@@ -228,6 +258,7 @@
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi3: spi@2130000 {
@@ -238,6 +269,7 @@
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi4: spi@2140000 {
@@ -248,6 +280,151 @@
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
+ };
+
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 23 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 23 0>;
+ assigned-clock-parents = <&k3_clks 23 1>;
+ power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 24 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 24 0>;
+ assigned-clock-parents = <&k3_clks 24 1>;
+ power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 27 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 27 0>;
+ assigned-clock-parents = <&k3_clks 27 1>;
+ power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 28 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 28 0>;
+ assigned-clock-parents = <&k3_clks 28 1>;
+ power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 29 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 29 0>;
+ assigned-clock-parents = <&k3_clks 29 1>;
+ power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 30 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 30 0>;
+ assigned-clock-parents = <&k3_clks 30 1>;
+ power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 31 0>;
+ assigned-clocks = <&k3_clks 31 0>;
+ assigned-clock-parents = <&k3_clks 31 1>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 32 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 32 0>;
+ assigned-clock-parents = <&k3_clks 32 1>;
+ power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer8: timer@2480000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2480000 0x00 0x400>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 33 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 33 0>;
+ assigned-clock-parents = <&k3_clks 33 1>;
+ power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer9: timer@2490000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2490000 0x00 0x400>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 34 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 34 0>;
+ assigned-clock-parents = <&k3_clks 34 1>;
+ power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer10: timer@24a0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24a0000 0x00 0x400>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 25 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 25 0>;
+ assigned-clock-parents = <&k3_clks 25 1>;
+ power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer11: timer@24b0000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x24b0000 0x00 0x400>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 26 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 26 0>;
+ assigned-clock-parents = <&k3_clks 26 1>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
};
sdhci0: mmc@4f80000 {
@@ -292,7 +469,6 @@
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,clkbuf-sel = <0x7>;
- ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@@ -304,21 +480,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
- pcie0_mode: pcie-mode@4060 {
- compatible = "syscon";
- reg = <0x00004060 0x4>;
- };
-
- pcie1_mode: pcie-mode@4070 {
- compatible = "syscon";
- reg = <0x00004070 0x4>;
- };
-
- pcie_devid: pcie-devid@210 {
- compatible = "syscon";
- reg = <0x00000210 0x4>;
- };
-
serdes0_clk: clock@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
@@ -338,11 +499,11 @@
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
- reg = <0x0000041e0 0x14>;
+ reg = <0x000041e0 0x14>;
};
- ehrpwm_tbclk: clock@4140 {
- compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ ehrpwm_tbclk: clock-controller@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
@@ -439,7 +600,7 @@
};
main_navss: bus@30800000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
@@ -497,6 +658,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -506,6 +668,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -515,6 +678,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -524,6 +688,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -533,6 +698,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -542,6 +708,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -551,6 +718,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -560,6 +728,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -569,6 +738,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -578,6 +748,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -587,6 +758,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -596,15 +768,17 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x3c000000 0x0 0x400000>,
- <0x0 0x38000000 0x0 0x400000>,
- <0x0 0x31120000 0x0 0x100>,
- <0x0 0x33000000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x3c000000 0x0 0x400000>,
+ <0x0 0x38000000 0x0 0x400000>,
+ <0x0 0x31120000 0x0 0x100>,
+ <0x0 0x33000000 0x0 0x40000>,
+ <0x0 0x31080000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
ti,num-rings = <818>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -614,9 +788,9 @@
main_udmap: dma-controller@31150000 {
compatible = "ti,am654-navss-main-udmap";
- reg = <0x0 0x31150000 0x0 0x100>,
- <0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -687,15 +861,15 @@
pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
- 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -703,32 +877,34 @@
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie0_ep: pcie-ep@5500000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
+ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4060>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
pcie1_rc: pcie@5600000 {
compatible = "ti,am654-pcie-rc";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
- 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
- ti,syscon-pcie-id = <&pcie_devid>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
+ <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&scm_conf 0x210>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@@ -736,19 +912,21 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
device_type = "pci";
+ status = "disabled";
};
pcie1_ep: pcie-ep@5600000 {
compatible = "ti,am654-pcie-ep";
- reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
+ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
- ti,syscon-pcie-mode = <&pcie1_mode>;
+ ti,syscon-pcie-mode = <&scm_conf 0x4070>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
};
mcasp0: mcasp@2b00000 {
@@ -766,6 +944,7 @@
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -783,6 +962,7 @@
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -800,6 +980,7 @@
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
cal: cal@6f03000 {
@@ -826,13 +1007,13 @@
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
- reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
- <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
- <0x0 0x04a06000 0x0 0x1000>, /* vid */
- <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
- <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
- <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
- <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
+ reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
+ <0x0 0x04a06000 0x0 0x1000>, /* vid */
+ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
+ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
+ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
+ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
@@ -840,9 +1021,9 @@
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 67 1>,
- <&k3_clks 216 1>,
- <&k3_clks 67 2>;
+ clocks = <&k3_clks 67 1>,
+ <&k3_clks 216 1>,
+ <&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
/*
@@ -870,6 +1051,7 @@
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm1: pwm@3010000 {
@@ -879,6 +1061,7 @@
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm2: pwm@3020000 {
@@ -888,6 +1071,7 @@
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm3: pwm@3030000 {
@@ -897,6 +1081,7 @@
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm4: pwm@3040000 {
@@ -906,6 +1091,7 @@
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm5: pwm@3050000 {
@@ -915,6 +1101,7 @@
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
icssg0: icssg@b000000 {
@@ -964,6 +1151,18 @@
};
};
+ icssg0_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
+ icssg0_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg0_iepclk_mux>;
+ };
+
icssg0_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1055,6 +1254,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1105,6 +1305,18 @@
};
};
+ icssg1_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
+ icssg1_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg1_iepclk_mux>;
+ };
+
icssg1_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1196,6 +1408,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1246,6 +1459,18 @@
};
};
+ icssg2_iep0: iep@2e000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2e000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
+ icssg2_iep1: iep@2f000 {
+ compatible = "ti,am654-icss-iep";
+ reg = <0x2f000 0x1000>;
+ clocks = <&icssg2_iepclk_mux>;
+ };
+
icssg2_mii_rt: mii-rt@32000 {
compatible = "ti,pruss-mii", "syscon";
reg = <0x32000 0x100>;
@@ -1337,6 +1562,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index c93ff1520a0..edd5cfbec40 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -20,13 +20,32 @@
};
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x10>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000101>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x8>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x00000003>;
+ };
+
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_ram: sram@41c00000 {
@@ -46,6 +65,7 @@
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_spi0: spi@40300000 {
@@ -56,6 +76,7 @@
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi1: spi@40310000 {
@@ -66,6 +87,7 @@
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi2: spi@40320000 {
@@ -76,6 +98,7 @@
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
tscadc0: tscadc@40200000 {
@@ -85,10 +108,11 @@
clocks = <&k3_clks 0 2>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7100>,
<&mcu_udmap 0x7101 >;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -103,10 +127,11 @@
clocks = <&k3_clks 1 2>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
- clock-names = "adc_tsc_fck";
+ clock-names = "fck";
dmas = <&mcu_udmap 0x7102>,
<&mcu_udmap 0x7103>;
dma-names = "fifo0", "fifo1";
+ status = "disabled";
adc {
#io-channel-cells = <1>;
@@ -114,8 +139,53 @@
};
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@40400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40400000 0x00 0x400>;
+ clocks = <&k3_clks 35 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@40410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40410000 0x00 0x400>;
+ clocks = <&k3_clks 36 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@40420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40420000 0x00 0x400>;
+ clocks = <&k3_clks 37 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@40430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x40430000 0x00 0x400>;
+ clocks = <&k3_clks 38 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -126,11 +196,13 @@
mcu_ringacc: ringacc@2b800000 {
compatible = "ti,am654-navss-ringacc";
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg",
+ "proxy_target", "cfg";
ti,num-rings = <286>;
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
ti,sci = <&dmsc>;
@@ -140,9 +212,9 @@
mcu_udmap: dma-controller@285c0000 {
compatible = "ti,am654-navss-mcu-udmap";
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -159,7 +231,54 @@
};
};
- fss: fss@47000000 {
+ secure_proxy_mcu: mailbox@2a480000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x0 0x2a480000 0x0 0x80000>,
+ <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
+ m_can0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40528000 0x0 0x400>,
+ <0x0 0x40500000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ m_can1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x0 0x40568000 0x0 0x400>,
+ <0x0 0x40540000 0x0 0x4400>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
+ clock-names = "hclk", "cclk";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -180,6 +299,7 @@
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
ospi1: spi@47050000 {
@@ -194,6 +314,7 @@
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -243,6 +364,7 @@
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
diff --git a/arch/arm/dts/k3-am65-wakeup.dtsi b/arch/arm/dts/k3-am65-wakeup.dtsi
index 9d21cdf6fce..fd2b998ebdd 100644
--- a/arch/arm/dts/k3-am65-wakeup.dtsi
+++ b/arch/arm/dts/k3-am65-wakeup.dtsi
@@ -12,8 +12,8 @@
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 11>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;
@@ -54,6 +54,7 @@
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
@@ -65,6 +66,7 @@
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
@@ -100,8 +102,4 @@
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
-
- thermal_zones: thermal-zones {
- #include "k3-am654-industrial-thermal.dtsi"
- };
};
diff --git a/arch/arm/dts/k3-am65.dtsi b/arch/arm/dts/k3-am65.dtsi
index a9fc1af03f2..4d7b6155a76 100644
--- a/arch/arm/dts/k3-am65.dtsi
+++ b/arch/arm/dts/k3-am65.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM654 SoC";
compatible = "ti,am654";
@@ -18,21 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- serial0 = &wkup_uart0;
- serial1 = &mcu_uart0;
- serial2 = &main_uart0;
- serial3 = &main_uart1;
- serial4 = &main_uart2;
- i2c0 = &wkup_i2c0;
- i2c1 = &mcu_i2c0;
- i2c2 = &main_i2c0;
- i2c3 = &main_i2c1;
- i2c4 = &main_i2c2;
- i2c5 = &main_i2c3;
- ethernet0 = &cpsw_port1;
- };
-
chosen { };
firmware {
@@ -84,6 +70,7 @@
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
index cfbcebfa37c..1637ec5ab5e 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -10,12 +10,25 @@
#include <dt-bindings/net/ti-dp83867.h>
/ {
- compatible = "ti,am654-evm", "ti,am654";
+ compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 Base Board";
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ ethernet0 = &cpsw_port1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@@ -73,20 +86,20 @@
pinctrl-names = "default";
pinctrl-0 = <&push_button_pins_default>;
- sw5 {
+ switch-5 {
label = "GPIO Key USER1";
linux,code = <BTN_0>;
gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
};
- sw6 {
+ switch-6 {
label = "GPIO Key USER2";
linux,code = <BTN_1>;
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
- evm_12v0: fixedregulator-evm12v0 {
+ evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@@ -96,7 +109,7 @@
regulator-boot-on;
};
- vcc3v3_io: fixedregulator-vcc3v3io {
+ vcc3v3_io: regulator-1 {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
@@ -107,7 +120,7 @@
vin-supply = <&evm_12v0>;
};
- vdd_mmc1_sd: fixedregulator-sd {
+ vdd_mmc1_sd: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
@@ -117,24 +130,53 @@
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
+
+ vtt_supply: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vtt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ };
};
&wkup_pmx0 {
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ };
+
+ ddr_vtt_pins_default: ddr-vtt-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
- push_button_pins_default: push-button-pins-default {
+ push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>;
};
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
@@ -150,13 +192,22 @@
>;
};
- wkup_pca554_default: wkup-pca554-default {
+ wkup_pca554_default: wkup-pca554-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
>;
};
- mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
@@ -173,16 +224,23 @@
>;
};
- mcu_mdio_pins_default: mcu-mdio1-pins-default {
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
+
+ mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
+ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
+ >;
+ };
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@@ -191,14 +249,14 @@
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
- main_spi0_pins_default: main-spi0-pins-default {
+ main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
@@ -207,7 +265,7 @@
>;
};
- main_mmc0_pins_default: main-mmc0-pins-default {
+ main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@@ -224,7 +282,7 @@
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@@ -237,7 +295,7 @@
>;
};
- usb1_pins_default: usb1-pins-default {
+ usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
@@ -245,21 +303,21 @@
};
&main_pmx1 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
- ecap0_pins_default: ecap0-pins-default {
+ ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@@ -269,19 +327,55 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
+ eeprom@50 {
+ /* AT24CM01 */
+ compatible = "atmel,24c1024";
+ reg = <0x50>;
+ };
+
+ vdd_mpu: regulator@60 {
+ compatible = "ti,tps62363";
+ reg = <0x60>;
+ regulator-name = "VDD_MPU";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1770000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+ ti,enable-vout-discharge;
+ };
+
+ gpio@38 {
+ compatible = "nxp,pca9554";
+ reg = <0x38>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
pca9554: gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
@@ -296,7 +390,15 @@
};
};
+&mcu_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -310,37 +412,39 @@
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
- #size-cells= <0>;
+ #size-cells = <0>;
ti,pindir-d0-out-d1-in;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
spi-max-frequency = <48000000>;
- #address-cells = <1>;
- #size-cells= <1>;
};
};
@@ -381,12 +485,14 @@
};
&tscadc0 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
+ status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
@@ -400,23 +506,8 @@
status = "disabled";
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -426,6 +517,7 @@
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -434,63 +526,24 @@
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
- mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
- mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
+ mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&ospi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- flash@0{
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -501,17 +554,65 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "ospi.tiboot3";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "ospi.tispl";
+ reg = <0x80000 0x200000>;
+ };
+
+ partition@280000 {
+ label = "ospi.u-boot";
+ reg = <0x280000 0x400000>;
+ };
+
+ partition@680000 {
+ label = "ospi.env";
+ reg = <0x680000 0x20000>;
+ };
+
+ partition@6a0000 {
+ label = "ospi.env.backup";
+ reg = <0x6a0000 0x20000>;
+ };
+
+ partition@6c0000 {
+ label = "ospi.sysfw";
+ reg = <0x6c0000 0x100000>;
+ };
+
+ partition@800000 {
+ label = "ospi.rootfs";
+ reg = <0x800000 0x37c0000>;
+ };
+
+ partition@3fe0000 {
+ label = "ospi.phypattern";
+ reg = <0x3fe0000 0x20000>;
+ };
+ };
};
};
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
@@ -524,30 +625,6 @@
phy-handle = <&phy0>;
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
&dss {
status = "disabled";
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
diff --git a/arch/arm/dts/k3-am654.dtsi b/arch/arm/dts/k3-am654.dtsi
index f0a6541b804..888567b921f 100644
--- a/arch/arm/dts/k3-am654.dtsi
+++ b/arch/arm/dts/k3-am654.dtsi
@@ -93,6 +93,7 @@
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -102,6 +103,7 @@
L2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
@@ -111,5 +113,10 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
+ cache-unified;
+ };
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
};
};
From b65ea697d7fc2b1a5661bde24bee39b4a7a176d9 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:02 -0600
Subject: [PATCH 15/40] arm: dts: k3-am654: copy bootph properties to a53 dts
In order to unify the R5 board dtb file with the Linux board dtb file,
we will need to copy all bootph-pre-ram properties to the *-u-boot.dtsi
overlay.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 160 +++++++++++++++++++
arch/arm/dts/k3-am654-r5-base-board.dts | 85 +---------
2 files changed, 162 insertions(+), 83 deletions(-)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index f29cecf870b..4b1e8ce2c92 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -5,6 +5,166 @@
#include "k3-am65x-binman.dtsi"
+&vtt_supply {
+ bootph-pre-ram;
+};
+
+&cbass_main {
+ bootph-pre-ram;
+};
+
+&main_navss {
+ bootph-pre-ram;
+};
+
+&cbass_mcu {
+ bootph-pre-ram;
+};
+
+&mcu_navss {
+ bootph-pre-ram;
+};
+
+&mcu_ringacc {
+ bootph-pre-ram;
+};
+
+&mcu_udmap {
+ bootph-pre-ram;
+};
+
+&wkup_gpio0 {
+ bootph-pre-ram;
+};
+
+&secure_proxy_main {
+ bootph-pre-ram;
+};
+
+&cbass_wakeup {
+ bootph-pre-ram;
+
+ chipid@43000014 {
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ bootph-pre-ram;
+};
+
+&k3_pds {
+ bootph-pre-ram;
+};
+
+&k3_clks {
+ bootph-pre-ram;
+};
+
+&k3_reset {
+ bootph-pre-ram;
+};
+
+&main_uart0 {
+ bootph-pre-ram;
+};
+
+&wkup_vtm0 {
+ bootph-pre-ram;
+};
+
+&wkup_pmx0 {
+ bootph-pre-ram;
+};
+
+&wkup_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&wkup_vtt_pins_default {
+ bootph-pre-ram;
+};
+
+&mcu_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-pre-ram;
+};
+
+&mcu_fss0_ospi0_pins_default {
+ bootph-pre-ram;
+};
+
+&main_pmx0 {
+ bootph-pre-ram;
+};
+
+&main_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&main_mmc0_pins_default {
+ bootph-pre-ram;
+};
+
+&main_mmc1_pins_default {
+ bootph-pre-ram;
+};
+
+&usb0_pins_default {
+ bootph-pre-ram;
+};
+
+&main_pmx1 {
+ bootph-pre-ram;
+};
+
+&sdhci0 {
+ bootph-pre-ram;
+};
+
+&sdhci1 {
+ bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+ bootph-pre-ram;
+};
+
+&vdd_mpu {
+ bootph-pre-ram;
+};
+
+&ospi0 {
+ bootph-pre-ram;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&dwc3_0 {
+ bootph-pre-ram;
+};
+
+&usb0_phy {
+ bootph-pre-ram;
+};
+
+&usb0 {
+ bootph-pre-ram;
+};
+
+&scm_conf {
+ bootph-pre-ram;
+};
+
+&fss {
+ bootph-pre-ram;
+};
+
&pru0_0 {
remoteproc-name = "pru0_0";
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index d75c7bf3fe6..8f55dab508e 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -53,13 +53,10 @@
regulator-max-microvolt = <3300000>;
gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
states = <0 0x0 3300000 0x1>;
- bootph-pre-ram;
};
};
&cbass_main {
- bootph-pre-ram;
-
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
@@ -67,15 +64,9 @@
clock-frequency = <25000000>;
bootph-all;
};
-
- main_navss: bus@30800000 {
- bootph-pre-ram;
- };
};
&cbass_mcu {
- bootph-pre-ram;
-
mcu_secproxy: secproxy@28380000 {
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
@@ -87,8 +78,6 @@
};
mcu_navss: bus@28380000 {
- bootph-pre-ram;
-
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
@@ -96,7 +85,6 @@
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- bootph-pre-ram;
ti,dma-ring-reset-quirk;
};
@@ -109,34 +97,11 @@
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- bootph-pre-ram;
};
};
};
-&k3_pds {
- bootph-pre-ram;
-};
-
-&k3_clks {
- bootph-pre-ram;
-};
-
-&k3_reset {
- bootph-pre-ram;
-};
-
-&wkup_gpio0 {
- bootph-pre-ram;
-};
-
-&secure_proxy_main {
- bootph-pre-ram;
-};
-
&cbass_wakeup {
- bootph-pre-ram;
-
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
@@ -150,40 +115,29 @@
clock-frequency = <200000000>;
bootph-pre-ram;
};
-
- chipid@43000014 {
- bootph-pre-ram;
- };
};
&dmsc {
- bootph-pre-ram;
-
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
-
- k3_sysreset: sysreset-controller {
- compatible = "ti,sci-sysreset";
- bootph-pre-ram;
- };
};
&wkup_uart0 {
- bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
+ bootph-pre-ram;
};
&mcu_uart0 {
- bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
/delete-property/ power-domains;
status = "okay";
+ bootph-pre-ram;
};
&main_uart0 {
@@ -191,18 +145,15 @@
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
status = "okay";
- bootph-pre-ram;
};
&wkup_vtm0 {
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
- bootph-pre-ram;
};
&wkup_pmx0 {
- bootph-pre-ram;
wkup_uart0_pins_default: wkup_uart0_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
@@ -210,14 +161,12 @@
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
- bootph-pre-ram;
};
wkup_vtt_pins_default: wkup_vtt_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
- bootph-pre-ram;
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
@@ -227,7 +176,6 @@
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
- bootph-pre-ram;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
@@ -235,7 +183,6 @@
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
- bootph-pre-ram;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
@@ -252,12 +199,10 @@
AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
>;
- bootph-pre-ram;
};
};
&main_pmx0 {
- bootph-pre-ram;
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
@@ -265,7 +210,6 @@
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
>;
- bootph-pre-ram;
};
main_mmc0_pins_default: main_mmc0_pins_default {
@@ -282,7 +226,6 @@
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
- bootph-pre-ram;
};
main_mmc1_pins_default: main_mmc1_pins_default {
@@ -296,21 +239,15 @@
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
>;
- bootph-pre-ram;
};
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
- bootph-pre-ram;
};
};
-&main_pmx1 {
- bootph-pre-ram;
-};
-
&memorycontroller {
vtt-supply = <&vtt_supply>;
pinctrl-names = "default";
@@ -323,7 +260,6 @@
pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
- bootph-pre-ram;
};
&sdhci1 {
@@ -332,14 +268,12 @@
pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
- bootph-pre-ram;
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
- bootph-pre-ram;
vdd_mpu: tps62363@60 {
compatible = "ti,tps62363";
@@ -351,7 +285,6 @@
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
- bootph-pre-ram;
};
};
@@ -376,23 +309,19 @@
cdns,read-delay = <0>;
#address-cells = <1>;
#size-cells = <1>;
- bootph-pre-ram;
};
};
&main_pmx0 {
- bootph-pre-ram;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
- bootph-pre-ram;
};
};
&dwc3_0 {
status = "okay";
- bootph-pre-ram;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
@@ -401,7 +330,6 @@
&usb0_phy {
status = "okay";
- bootph-pre-ram;
/delete-property/ clocks;
};
@@ -409,11 +337,6 @@
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
- bootph-pre-ram;
-};
-
-&scm_conf {
- bootph-pre-ram;
};
&davinci_mdio {
@@ -441,7 +364,3 @@
&usb1 {
dr_mode = "peripheral";
};
-
-&fss {
- bootph-pre-ram;
-};
From e72ece589423128b24df86796c87171a9d641fac Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:03 -0600
Subject: [PATCH 16/40] arm: dts: k3-am654: include a53 board dtb for r5 build
To make things as organized as possible, start from the Linux board dtbs
and apply all properties needed for U-Boot in our *-u-boot.dtsi file for
the MAIN SPL and U-Boot builds.
We can then include these files for the WKUP SPL build making further
edits to the needed properties and nodes for the WKUP SPL bootloader's
view of the am65x.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 8f55dab508e..79ca6387c22 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -5,7 +5,8 @@
/dts-v1/;
-#include "k3-am654.dtsi"
+#include "k3-am654-base-board.dts"
+#include "k3-am654-base-board-u-boot.dtsi"
#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
#include "k3-am654-ddr.dtsi"
From a67443efc707d9c20e75e73e347d2169799f1868 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:04 -0600
Subject: [PATCH 17/40] arm: dts: k3-am654: remove duplicate vtt_supply
With the Linux and U-Boot board dtb files unified we now have a
duplicate vtt_supply node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 79ca6387c22..50e6be61182 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -46,15 +46,6 @@
ti,sci-host-id = <10>;
bootph-pre-ram;
};
-
- vtt_supply: vtt_supply {
- compatible = "regulator-gpio";
- regulator-name = "vtt";
- regulator-min-microvolt = <0>;
- regulator-max-microvolt = <3300000>;
- gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
- states = <0 0x0 3300000 0x1>;
- };
};
&cbass_main {
From 3bf9f9a35f550dfccea47b75586a956a590b303b Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:05 -0600
Subject: [PATCH 18/40] arm: dts: k3-am654: remove duplicate wkup_uart0
With the Linux and U-Boot board files unified, we now have a duplicate
wkup_uart0 node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 50e6be61182..fb13a17b1dc 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -18,7 +18,6 @@
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
spi0 = &ospi0;
@@ -117,8 +116,6 @@
};
&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
@@ -146,15 +143,6 @@
};
&wkup_pmx0 {
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
- AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
- AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
- >;
- };
-
wkup_vtt_pins_default: wkup_vtt_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
From 7cf2fa8096414be4161f0dad8515ddf2ad3fc0f4 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:06 -0600
Subject: [PATCH 19/40] arm: dts: k3-am654: remove duplicate timer
timer1 is really just the mcu_timer0 node redefined for the WKUP SPL.
Remove the timer1 and replace it with the mcu_timer0 from the Linux
device tree we imported into U-Boot.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 12 ++++++++
arch/arm/dts/k3-am654-r5-base-board.dts | 30 ++++++++++----------
2 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 4b1e8ce2c92..a008af5b4a0 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -5,6 +5,18 @@
#include "k3-am65x-binman.dtsi"
+/ {
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+};
+
+&mcu_timer0 {
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ bootph-all;
+};
+
&vtt_supply {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index fb13a17b1dc..f462262b9aa 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -26,11 +26,6 @@
usb1 = &usb1;
};
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
@@ -47,16 +42,6 @@
};
};
-&cbass_main {
- timer1: timer@40400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x40400000 0x0 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-all;
- };
-};
-
&cbass_mcu {
mcu_secproxy: secproxy@28380000 {
compatible = "ti,am654-secure-proxy";
@@ -108,6 +93,21 @@
};
};
+/*
+ * timer init is called as part of rproc_start() while
+ * starting System Firmware, so any clock/power-domain
+ * operations will fail as SYSFW is not yet up and running.
+ * Delete all clock/power-domain properties to avoid
+ * timer init failure.
+ * This is an always on timer at 20MHz.
+ */
+&mcu_timer0 {
+ /delete-property/ clocks;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
+};
+
&dmsc {
mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx", "notify";
From afb7fb6ba7c63ce6eeed3c52bd2ddf7e29e44521 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:07 -0600
Subject: [PATCH 20/40] arm: dts: k3-am654: remove duplicate mcu_ringacc
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu_ringacc node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index f462262b9aa..c4fa84a3d0b 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -54,16 +54,6 @@
};
mcu_navss: bus@28380000 {
- ringacc@2b800000 {
- reg = <0x0 0x2b800000 0x0 0x400000>,
- <0x0 0x2b000000 0x0 0x400000>,
- <0x0 0x28590000 0x0 0x100>,
- <0x0 0x2a500000 0x0 0x40000>,
- <0x0 0x28440000 0x0 0x40000>;
- reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- ti,dma-ring-reset-quirk;
- };
-
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
From 194641300c1679cb53ea5399251df21cf94611ef Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:08 -0600
Subject: [PATCH 21/40] arm: dts: k3-am654: remove duplicate mcu_udmap
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu_udmap node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index c4fa84a3d0b..19806ec4e23 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -52,19 +52,6 @@
#mbox-cells = <1>;
bootph-pre-ram;
};
-
- mcu_navss: bus@28380000 {
- dma-controller@285c0000 {
- reg = <0x0 0x285c0000 0x0 0x100>,
- <0x0 0x284c0000 0x0 0x4000>,
- <0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x284a0000 0x0 0x4000>,
- <0x0 0x2aa00000 0x0 0x40000>,
- <0x0 0x28400000 0x0 0x2000>;
- reg-names = "gcfg", "rchan", "rchanrt", "tchan",
- "tchanrt", "rflow";
- };
- };
};
&cbass_wakeup {
From 5e00547e583f6d4349f3908d3491bf6ce0a8818c Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:09 -0600
Subject: [PATCH 22/40] arm: dts: k3-am654: add needed regs to udmap nodes
Ethernet is one of a few IPs in U-Boot that depend on DMA to operate.
However there are a few missing registers ranges in the udmap nodes
need to properly setup DMA for the am65x.
A fix has been added to the Linux kernel[0] to add these ranges however
they have not made it to a Linux tag. To keep DMA operational until the
next DT sync from Linux, add these ranges to the *-u-boot.dtsi with a
note for our future selves.
[0] https://lore.kernel.org/r/20231213135138.929517-2-vigneshr@ti.com
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 34 ++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index a008af5b4a0..a24cb895e55 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -252,3 +252,37 @@
&mcu_r5fss0 {
ti,cluster-mode = <0>;
};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&main_udmap {
+ reg = <0x0 0x31150000 0x0 0x100>,
+ <0x0 0x34000000 0x0 0x100000>,
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x10000>,
+ <0x0 0x30c00000 0x0 0x10000>,
+ <0x0 0x30d00000 0x0 0x8000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
+
+/*
+ * The DMA driver requires a few extra register ranges
+ * which are missing for the am65x. A patch has been
+ * sent and will be synced after the v6.8-rc1 linux
+ * tag is published
+ */
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
+};
From bdf8a2c0405a3436baba750ef4c738fac44c0f96 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:10 -0600
Subject: [PATCH 23/40] arm: dts: k3-am654: remove duplicate mcu_uart0 node
With the Linux and U-Boot board dtb files unified we now have a
duplicate mcu_uart0 node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 19806ec4e23..bdee47802b0 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -18,7 +18,6 @@
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial1 = &mcu_uart0;
serial2 = &main_uart0;
spi0 = &ospi0;
spi1 = &ospi1;
@@ -98,8 +97,6 @@
};
&mcu_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
/delete-property/ power-domains;
status = "okay";
@@ -126,15 +123,6 @@
>;
};
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
- >;
- };
-
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
From 3e00c8b82e890ca1a7dadd9aadd29cf1e8d8a8ec Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:11 -0600
Subject: [PATCH 24/40] arm: dts: k3-am654: remove duplicate main_uart0
With the Linux and U-Boot board dtb files unified, we now have a
duplicate main_uart0 node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index bdee47802b0..3d599a54138 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -18,7 +18,6 @@
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial2 = &main_uart0;
spi0 = &ospi0;
spi1 = &ospi1;
usb0 = &usb0;
@@ -103,13 +102,6 @@
bootph-pre-ram;
};
-&main_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
- status = "okay";
-};
-
&wkup_vtm0 {
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
@@ -148,15 +140,6 @@
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
- AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
- AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
- AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
- >;
- };
-
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
From 52d87efd0203a13cee5568e55767a92959fbe728 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:12 -0600
Subject: [PATCH 25/40] arm: dts: k3-am654: remove duplicate sdhci0 pinmux node
With the Linux and U-Boot board dtb files unified, we now have
a duplicate sdhci0 pinmux node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 26 ++++++++-----------------
1 file changed, 8 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 3d599a54138..f28245b12b6 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -140,22 +140,6 @@
};
&main_pmx0 {
- main_mmc0_pins_default: main_mmc0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
- AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
- AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
- AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
- AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
- AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
- AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
- AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
- AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
- AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
- AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
- >;
- };
-
main_mmc1_pins_default: main_mmc1_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
@@ -182,12 +166,18 @@
pinctrl-0 = <&wkup_vtt_pins_default>;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc0_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
};
&sdhci1 {
From 7f66ec50adc9874e2beccaf371cc2fe05cbf527e Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:13 -0600
Subject: [PATCH 26/40] arm: dts: k3-am654: remove duplicate sdhci1 pinmux node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate sdhci1 pinmux node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index f28245b12b6..9d7467acd30 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -140,19 +140,6 @@
};
&main_pmx0 {
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
- AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
- AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
- AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
- AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
- AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
- AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
- AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
- >;
- };
-
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
@@ -180,12 +167,18 @@
/delete-property/ power-domains;
};
+/*
+ * MMC is probed to pull in firmware, so any clock
+ * or power-domain operation will fail as we do not
+ * have the firmware running at this point. Delete the
+ * power-domain properties to avoid making calls to
+ * SYSFW before it is loaded. Public ROM has already
+ * set it up for us anyway.
+ */
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
- pinctrl-0 = <&main_mmc1_pins_default>;
/delete-property/ power-domains;
- ti,driver-strength-ohm = <50>;
};
&wkup_i2c0 {
From 41ae2c6fb7c717aa92713a1362cb743d7ee6004f Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:14 -0600
Subject: [PATCH 27/40] arm: dts: k3-am654: remove duplicate wkup_i2c0
With the Linux and U-Boot board dtb files unified, we now have a
duplicate wkup_i2c0 node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 25 -------------------------
1 file changed, 25 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 9d7467acd30..8c6cb147c82 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -115,13 +115,6 @@
>;
};
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
- AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
- >;
- };
-
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
@@ -181,24 +174,6 @@
/delete-property/ power-domains;
};
-&wkup_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- vdd_mpu: tps62363@60 {
- compatible = "ti,tps62363";
- reg = <0x60>;
- regulator-name = "VDD_MPU";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1770000>;
- regulator-always-on;
- regulator-boot-on;
- ti,vsel0-state-high;
- ti,vsel1-state-high;
- };
-};
-
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
From 755db5fc7c0188358e94e1b67020011fb46cd521 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:15 -0600
Subject: [PATCH 28/40] arm: dts: k3-am654: remove duplicate ospi0 node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate ospi0 node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 37 -------------------------
1 file changed, 37 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 8c6cb147c82..da41971a78f 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -18,8 +18,6 @@
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- spi0 = &ospi0;
- spi1 = &ospi1;
usb0 = &usb0;
usb1 = &usb1;
};
@@ -114,22 +112,6 @@
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
};
-
- mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
- AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
- AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
- AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
- AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
- AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
- AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
- AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
- AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
- AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
- AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
- >;
- };
};
&main_pmx0 {
@@ -175,27 +157,8 @@
};
&ospi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
- bootph-pre-ram;
-
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
-
- flash@0{
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <50000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
};
&main_pmx0 {
From 9a6fab6d820c3923888402c4516ed271ee040564 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:16 -0600
Subject: [PATCH 29/40] arm: dts: k3-am654: remove usb0
The pinmux for usb0 is missing from the Linux board dtb file. Remove it
until we can introduce it in Linux
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 12 --------
arch/arm/dts/k3-am654-r5-base-board.dts | 29 --------------------
2 files changed, 41 deletions(-)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index a24cb895e55..3647088c29e 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -125,10 +125,6 @@
bootph-pre-ram;
};
-&usb0_pins_default {
- bootph-pre-ram;
-};
-
&main_pmx1 {
bootph-pre-ram;
};
@@ -161,14 +157,6 @@
bootph-pre-ram;
};
-&usb0_phy {
- bootph-pre-ram;
-};
-
-&usb0 {
- bootph-pre-ram;
-};
-
&scm_conf {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index da41971a78f..8e57c77cba9 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -18,8 +18,6 @@
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- usb0 = &usb0;
- usb1 = &usb1;
};
a53_0: a53@0 {
@@ -114,14 +112,6 @@
};
};
-&main_pmx0 {
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- };
-};
-
&memorycontroller {
vtt-supply = <&vtt_supply>;
pinctrl-names = "default";
@@ -161,14 +151,6 @@
<0x0 0x50000000 0x0 0x8000000>;
};
-&main_pmx0 {
- usb0_pins_default: usb0_pins_default {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
- >;
- };
-};
-
&dwc3_0 {
status = "okay";
/delete-property/ clocks;
@@ -177,17 +159,6 @@
/delete-property/ assigned-clock-parents;
};
-&usb0_phy {
- status = "okay";
- /delete-property/ clocks;
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins_default>;
- dr_mode = "peripheral";
-};
-
&davinci_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
From c7b075074f0c3adef3c64c6e5c69e2bd9a855508 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:17 -0600
Subject: [PATCH 30/40] arm: dts: k3-am654: remove duplicate mdio
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mdio node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 8e57c77cba9..14bf1b4c8a4 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -159,15 +159,6 @@
/delete-property/ assigned-clock-parents;
};
-&davinci_mdio {
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
&mcu_cpsw {
reg = <0x0 0x46000000 0x0 0x200000>,
<0x0 0x40f00200 0x0 0x2>;
From d23582d052e4d5a0f1e782b64efca1d8a081332e Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:18 -0600
Subject: [PATCH 31/40] arm: dts: k3-am654: remove duplicate vtt pinmux
With the Linux and U-Boot board dtb files unified, we now have a
duplicate vtt_pinmux node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-am654-r5-base-board.dts | 10 ----------
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 3647088c29e..da6d4dffbf9 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -93,7 +93,7 @@
bootph-pre-ram;
};
-&wkup_vtt_pins_default {
+&ddr_vtt_pins_default {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 14bf1b4c8a4..fb238adaea5 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -104,18 +104,8 @@
vdd-supply-4 = <&vdd_mpu>;
};
-&wkup_pmx0 {
- wkup_vtt_pins_default: wkup_vtt_pins_default {
- pinctrl-single,pins = <
- AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
- >;
- };
-};
-
&memorycontroller {
vtt-supply = <&vtt_supply>;
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_vtt_pins_default>;
};
/*
From dabf30a2bf95a3236e5a54a944c37505ea7027a9 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:19 -0600
Subject: [PATCH 32/40] arm: dts: k3-am654: remove duplicate root properties
With the Linux and U-Boot board dtb files unified, we have duplicate
properties in the root node. Remove them
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index fb238adaea5..c039300c3cb 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -11,9 +11,6 @@
#include "k3-am654-ddr.dtsi"
/ {
- compatible = "ti,am654-evm", "ti,am654";
- model = "Texas Instruments AM654 R5 Base Board";
-
aliases {
ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
From 5baad5521d271cc980804d2ff26adf3e14d711eb Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:20 -0600
Subject: [PATCH 33/40] arm: dts: k3-am654: remove un-needed aliases
These aliases are not needed in U-Boot. Remove them
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index c039300c3cb..9926981c661 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -12,7 +12,6 @@
/ {
aliases {
- ethernet0 = &cpsw_port1;
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
From e055622bd7f42810b2f329ec60596dfa62952d69 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:21 -0600
Subject: [PATCH 34/40] arm: dts: k3-am654: move dummy_clock to root node
The dummy_clock node is used to help the drivers probe the IO needed to
setup consoles and boot media to load firmware into the SoC.
This dummy_clock isn't a device that exists nor does it exist in the
mcu domain. So move it from cbass_mcu to the root node to avoid any
confusion.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 9926981c661..b27b2b05ad8 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -30,6 +30,13 @@
ti,sci-host-id = <10>;
bootph-pre-ram;
};
+
+ clk_200mhz: dummy_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ bootph-pre-ram;
+ };
};
&cbass_mcu {
@@ -51,13 +58,6 @@
mbox-names = "tx", "rx";
bootph-pre-ram;
};
-
- clk_200mhz: dummy_clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- bootph-pre-ram;
- };
};
/*
From 4aea536754a5764c7357032e5ade0d08392114e8 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:22 -0600
Subject: [PATCH 35/40] arm: dts: k3-am654: remove duplicate mcu secure proxy
node
With the Linux and U-Boot board dtb files unified, we now have a
duplicate mcu secure proxy node. Remove it
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-r5-base-board.dts | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index b27b2b05ad8..dea2ba85dcb 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -39,22 +39,15 @@
};
};
-&cbass_mcu {
- mcu_secproxy: secproxy@28380000 {
- compatible = "ti,am654-secure-proxy";
- reg = <0x0 0x2a380000 0x0 0x80000>,
- <0x0 0x2a400000 0x0 0x80000>,
- <0x0 0x2a480000 0x0 0x80000>;
- reg-names = "rt", "scfg", "target_data";
- #mbox-cells = <1>;
- bootph-pre-ram;
- };
+&secure_proxy_mcu {
+ status = "okay";
+ bootph-pre-ram;
};
&cbass_wakeup {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
- mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
@@ -76,7 +69,9 @@
};
&dmsc {
- mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mboxes = <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 6>,
+ <&secure_proxy_mcu 5>;
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
From 37a1a4074b83fbd8504ac446fdee300a88e35551 Mon Sep 17 00:00:00 2001
From: Bryan Brattlof <bb@ti.com>
Date: Fri, 29 Dec 2023 11:47:23 -0600
Subject: [PATCH 36/40] arm: dts: k3-am654: convert bootph-pre-ram to
bootph-all
Many nodes are reused between WKUP SPL, MAIN SPL, and U-Boot. Using
bootph-pre-ram is causing these nodes to be present in SPL builds but
pruned away during the U-Boot build. Convert these nodes to bootph-all
so they will remain no matter which dtb build is happening.
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 74 ++++++++++----------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index da6d4dffbf9..4fd188fa191 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -18,151 +18,151 @@
};
&vtt_supply {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_main {
- bootph-pre-ram;
+ bootph-all;
};
&main_navss {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_navss {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_ringacc {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_udmap {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
chipid@43000014 {
- bootph-pre-ram;
+ bootph-all;
};
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_vtm0 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_uart0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&ddr_vtt_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_uart0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_fss0_ospi0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx1 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci0 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&vdd_mpu {
- bootph-pre-ram;
+ bootph-all;
};
&ospi0 {
- bootph-pre-ram;
+ bootph-all;
flash@0 {
- bootph-pre-ram;
+ bootph-all;
};
};
&dwc3_0 {
- bootph-pre-ram;
+ bootph-all;
};
&scm_conf {
- bootph-pre-ram;
+ bootph-all;
};
&fss {
- bootph-pre-ram;
+ bootph-all;
};
&pru0_0 {
From 244c9fd1a540b5ac7c4a67c8e8acfb0690a2075b Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Mon, 13 Nov 2023 08:51:42 -0600
Subject: [PATCH 37/40] arm: mach-k3: am62a: Add main_timer0 id to the dev list
main_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices list so it an be enabled via the k3 power controller.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
---
arch/arm/mach-k3/am62ax/dev-data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c
index abf5d8e91aa..6cced9efd08 100644
--- a/arch/arm/mach-k3/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/am62ax/dev-data.c
@@ -52,6 +52,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(161, &soc_lpsc_list[5]),
PSC_DEV(162, &soc_lpsc_list[6]),
PSC_DEV(75, &soc_lpsc_list[7]),
+ PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
PSC_DEV(166, &soc_lpsc_list[9]),
From e703bfcb38ce837c5fd9e12ad15412eae951a7d7 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Mon, 13 Nov 2023 08:51:43 -0600
Subject: [PATCH 38/40] arm: dts: k3-am62a*: Sync with kernel v6.7-rc1
Sync with kernel v6.7-rc1 and sync up the u-boot dts files accordingly.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/dts/k3-am62a-main.dtsi | 585 +++++++++++++++++++++++++-
arch/arm/dts/k3-am62a-mcu.dtsi | 131 ++++++
arch/arm/dts/k3-am62a-thermal.dtsi | 47 +++
arch/arm/dts/k3-am62a-wakeup.dtsi | 21 +-
arch/arm/dts/k3-am62a.dtsi | 5 +-
arch/arm/dts/k3-am62a7-r5-sk.dts | 74 +---
arch/arm/dts/k3-am62a7-sk-u-boot.dtsi | 139 ++++--
arch/arm/dts/k3-am62a7-sk.dts | 347 ++++++++++++++-
arch/arm/dts/k3-am62a7.dtsi | 3 +-
9 files changed, 1224 insertions(+), 128 deletions(-)
create mode 100644 arch/arm/dts/k3-am62a-thermal.dtsi
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
index bc4b50bcd17..4ae7fdc5221 100644
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ b/arch/arm/dts/k3-am62a-main.dtsi
@@ -48,6 +48,18 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
dmss: bus@48000000 {
@@ -69,6 +81,67 @@
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <6 70 34>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
};
dmsc: system-controller@44043000 {
@@ -77,8 +150,8 @@
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
@@ -96,6 +169,21 @@
};
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -104,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -222,6 +406,39 @@
status = "disabled";
};
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ status = "disabled";
+ };
+
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
@@ -295,4 +512,368 @@
no-1-8-v;
status = "disabled";
};
+
+ usbss0: dwc3-usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>;
+ clocks = <&k3_clks 161 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: dwc3-usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>;
+ clocks = <&k3_clks 162 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster1: mailbox@29010000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29010000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ main_mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&k3_clks 125 0>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 125 0>;
+ assigned-clock-parents = <&k3_clks 125 2>;
+ };
+
+ main_rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&k3_clks 126 0>;
+ power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 126 0>;
+ assigned-clock-parents = <&k3_clks 126 2>;
+ };
+
+ main_rti2: watchdog@e020000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e020000 0x00 0x100>;
+ clocks = <&k3_clks 127 0>;
+ power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 127 0>;
+ assigned-clock-parents = <&k3_clks 127 2>;
+ };
+
+ main_rti3: watchdog@e030000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e030000 0x00 0x100>;
+ clocks = <&k3_clks 128 0>;
+ power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 128 0>;
+ assigned-clock-parents = <&k3_clks 128 2>;
+ };
+
+ main_rti4: watchdog@e040000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e040000 0x00 0x100>;
+ clocks = <&k3_clks 205 0>;
+ power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 205 0>;
+ assigned-clock-parents = <&k3_clks 205 2>;
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp0: audio-controller@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 190 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 190 0>;
+ assigned-clock-parents = <&k3_clks 190 2>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: audio-controller@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 191 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 191 0>;
+ assigned-clock-parents = <&k3_clks 191 2>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: audio-controller@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 192 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 192 0>;
+ assigned-clock-parents = <&k3_clks 192 2>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi
index 6d1e501b94a..a6d16a94088 100644
--- a/arch/arm/dts/k3-am62a-mcu.dtsi
+++ b/arch/arm/dts/k3-am62a-mcu.dtsi
@@ -15,6 +15,51 @@
status = "disabled";
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@@ -36,4 +81,90 @@
clock-names = "fck";
status = "disabled";
};
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ status = "disabled";
+ };
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x04201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <24>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ mcu_rti0: watchdog@4880000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x04880000 0x00 0x100>;
+ clocks = <&k3_clks 131 0>;
+ power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 131 0>;
+ assigned-clock-parents = <&k3_clks 131 2>;
+ /* Tightly coupled to M4F */
+ status = "reserved";
+ };
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi
new file mode 100644
index 00000000000..85ce545633e
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi
index 99afac40e8d..4e8279fa01e 100644
--- a/arch/arm/dts/k3-am62a-wakeup.dtsi
+++ b/arch/arm/dts/k3-am62a-wakeup.dtsi
@@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
+
+ wkup_rti0: watchdog@2b000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2b000000 0x00 0x100>;
+ clocks = <&k3_clks 132 0>;
+ power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 132 0>;
+ assigned-clock-parents = <&k3_clks 132 2>;
+ /* Used by DM firmware */
+ status = "reserved";
+ };
+
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi
index 6eb87c3f9f3..61a210ecd5f 100644
--- a/arch/arm/dts/k3-am62a.dtsi
+++ b/arch/arm/dts/k3-am62a.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
@@ -114,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
+
+ #include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index bbbd9e51d69..bc05dcb5efb 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -7,7 +7,6 @@
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
@@ -15,33 +14,6 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial0 = &wkup_uart0;
- serial3 = &main_uart1;
- };
-
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
};
a53_0: a53@0 {
@@ -81,67 +53,39 @@
ti,secure-host;
};
-&cbass_main {
- sa3_secproxy: secproxy@44880000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg = <0x00 0x44880000 0x00 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- bootph-pre-ram;
- };
+&secure_proxy_sa3 {
+ /* Needed for initial handshake with ROM */
+ status = "okay";
+ bootph-pre-ram;
+};
+&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
- <&sa3_secproxy 0>;
+ <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
-&mcu_pmx0 {
- status = "okay";
+&wkup_uart0_pins_default {
bootph-pre-ram;
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
- >;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&main_uart1_pins_default {
bootph-pre-ram;
- main_uart1_pins_default: main-uart1-pins-default {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
- >;
- bootph-pre-ram;
- };
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index cf938c43b83..31b89b41748 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -4,137 +4,186 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "k3-am62a-sk-binman.dtsi"
+
/ {
chosen {
stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
-&cbass_main{
- bootph-pre-ram;
+&main_timer0 {
+ bootph-all;
+};
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x00 0x2400000 0x00 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
+&cbass_main {
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_uart1 {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&exp1 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&vdd_mmc1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&cpsw_port1 {
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index 270e669f655..8f64ac2c756 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -9,15 +9,17 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
+ compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
+ serial0 = &wkup_uart0;
serial2 = &main_uart0;
+ serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@@ -77,10 +79,10 @@
regulator-boot-on;
};
- vcc_3v3_sys: regulator-2 {
+ vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
+ regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
@@ -99,6 +101,17 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
+ vcc_3v3_sys: regulator-4 {
+ /* output of TPS222965DSGT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -112,38 +125,100 @@
default-state = "off";
};
};
+
+ tlv320_mclk: clk-0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ };
+
+ codec_audio: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM62Ax-SKEVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&tlv320_mclk>;
+ };
+ };
+};
+
+&mcu_pmx0 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
+ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
+ AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
+ AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
+ >;
+ };
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
};
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
+ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
+ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
+ AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
+ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@@ -155,11 +230,64 @@
>;
};
- usr_led_pins_default: usr-led-pins-default {
+ usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+ AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+ AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+ AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+ AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+ AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+ AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+ AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+ AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
+ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
+ AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ status = "okay";
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
+ >;
+ };
+};
+
+&mcu_gpio0 {
+ status = "okay";
};
&main_i2c0 {
@@ -167,13 +295,112 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+
+ typec_pd0: usb-power-controller@3f {
+ compatible = "ti,tps6598x";
+ reg = <0x3f>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ self-powered;
+ data-role = "dual";
+ power-role = "sink";
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
+ };
+ };
+ };
+ };
+
+ tps659312: pmic@48 {
+ compatible = "ti,tps6593-q1";
+ reg = <0x48>;
+ ti,primary-pmic;
+ system-power-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&mcu_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ buck123-supply = <&vcc_3v3_sys>;
+ buck4-supply = <&vcc_3v3_sys>;
+ buck5-supply = <&vcc_3v3_sys>;
+ ldo1-supply = <&vcc_3v3_sys>;
+ ldo2-supply = <&vcc_3v3_sys>;
+ ldo3-supply = <&buck5>;
+ ldo4-supply = <&vcc_3v3_sys>;
+
+ regulators {
+ buck123: buck123 {
+ regulator-name = "vcc_core";
+ regulator-min-microvolt = <715000>;
+ regulator-max-microvolt = <895000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-name = "vcc_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-name = "vcc_1v8_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: ldo1 {
+ regulator-name = "vddshv5_sdio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: ldo2 {
+ regulator-name = "vpp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: ldo3 {
+ regulator-name = "vcc_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: ldo4 {
+ regulator-name = "vdda_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
@@ -194,6 +421,19 @@
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
+
+ tlv320aic3106: audio-codec@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+
+ /* Regulators */
+ AVDD-supply = <&vcc_3v3_sys>;
+ IOVDD-supply = <&vcc_3v3_sys>;
+ DRVDD-supply = <&vcc_3v3_sys>;
+ DVDD-supply = <&buck5>;
+ };
};
&sdhci1 {
@@ -223,3 +463,84 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "reserved";
+};
+
+&usbss0 {
+ status = "okay";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ usb-role-switch;
+
+ port {
+ usb0_hs_ep: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
index 331d89fda29..58f1c43edcf 100644
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ b/arch/arm/dts/k3-am62a7.dtsi
@@ -95,8 +95,9 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
From b2cbf968dd68b1e2ca60f1186844862d3bbe48bc Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 3 Jan 2024 09:09:56 -0500
Subject: [PATCH 39/40] configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/imx8mm_data_modul_edm_sbc_defconfig | 2 --
configs/imx8mp_data_modul_edm_sbc_defconfig | 2 --
configs/imx8mp_dhcom_pdk2_defconfig | 2 --
configs/imx8mp_dhcom_pdk3_defconfig | 2 --
configs/x96_mate_defconfig | 2 +-
5 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 06e10869bc1..d61f8393a24 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -119,7 +119,6 @@ CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -172,7 +171,6 @@ CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 3974e376b85..cc7d5623ba3 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -125,7 +125,6 @@ CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -184,7 +183,6 @@ CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index e072d7adca0..dc482abad85 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -120,7 +120,6 @@ CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -180,7 +179,6 @@ CONFIG_DM_I2C=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index d0ace794bb2..3442af6f00e 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -122,7 +122,6 @@ CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
@@ -185,7 +184,6 @@ CONFIG_I2C_MUX_PCA954x=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig
index e805e0952b3..42a3b8c1310 100644
--- a/configs/x96_mate_defconfig
+++ b/configs/x96_mate_defconfig
@@ -18,7 +18,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
-CONFIG_AXP305_POWER=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_AXP305_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
From 80cb22c58bd9ec11e970bae84510a99171b691eb Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Wed, 3 Jan 2024 09:11:33 -0500
Subject: [PATCH 40/40] Prepare v2024.01-rc6
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Makefile | 2 +-
doc/develop/release_cycle.rst | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 220411a293f..0cac324fe00 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
NAME =
# *DOCUMENTATION*
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 8fe77f23b6e..0cd83df8b74 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -74,7 +74,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
-.. * U-Boot v2024.01-rc6 was released on Tue 02 January 2024.
+* U-Boot v2024.01-rc6 was released on Wed 03 January 2024.
Please note that the following dates are planned only and may be deviated from
as needed.