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dm: misc: bind STM32F4/F7 clock from rcc MFD driver

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Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
Patrice Chotard 2017-11-15 13:14:51 +01:00 • committed by Tom Rini
parent fe8d4780ff
commit 928954fe58
3 changed files with 102 additions and 46 deletions
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52
include/stm32_rcc.h Normal file
View file

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/*
* Copyright (C) STMicroelectronics SA 2017
* Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __STM32_RCC_H_
#define __STM32_RCC_H_
#define AHB_PSC_1 0
#define AHB_PSC_2 0x8
#define AHB_PSC_4 0x9
#define AHB_PSC_8 0xA
#define AHB_PSC_16 0xB
#define AHB_PSC_64 0xC
#define AHB_PSC_128 0xD
#define AHB_PSC_256 0xE
#define AHB_PSC_512 0xF
#define APB_PSC_1 0
#define APB_PSC_2 0x4
#define APB_PSC_4 0x5
#define APB_PSC_8 0x6
#define APB_PSC_16 0x7
struct pll_psc {
u8 pll_m;
u16 pll_n;
u8 pll_p;
u8 pll_q;
u8 ahb_psc;
u8 apb1_psc;
u8 apb2_psc;
};
struct stm32_clk_info {
struct pll_psc sys_pll_psc;
bool has_overdrive;
};
enum soc_family {
STM32F4,
STM32F7,
};
struct stm32_rcc_clk {
char *drv_name;
enum soc_family soc;
};
#endif /* __STM32_RCC_H_ */