Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-05-08 10:39:08 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

mpc83xx: Fix the incorrect dcbz operation

Browse source 
The 834x rev1.x silicon has one CPU5 errata.

The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.

The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.

The 834x rev3.0 and later and 8360 have not this bug inside.

So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.

However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.

This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.

CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.

Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu 2006-11-02 18:05:50 -06:00 • committed by Kim Phillips
parent bf0b542d67
commit 90f30a710a
4 changed files with 39 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

5
include/common.h
View file

@ -402,6 +402,11 @@ void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
#if defined (CONFIG_MPC83XX)
void ppcDWload(unsigned int *addr, unsigned int *ret);
void ppcDWstore(unsigned int *addr, unsigned int *value);
#endif
/* $(CPU)/cpu.c */
int checkcpu (void);
int checkicache (void);